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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-05-03 12:25:20 -0700 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-05-03 12:25:20 -0700 |
| commit | a0818796b4ad4340812805bdc9d4281786ab9cf4 (patch) | |
| tree | 8d090498a68484f526360cb8448051415602fd2b /model/riscv_insts_next.sail | |
| parent | 8f89e8a877f93a2bafbe2e7e42b4bccd30ba45f9 (diff) | |
| download | sail-riscv-a0818796b4ad4340812805bdc9d4281786ab9cf4.zip sail-riscv-a0818796b4ad4340812805bdc9d4281786ab9cf4.tar.gz sail-riscv-a0818796b4ad4340812805bdc9d4281786ab9cf4.tar.bz2 | |
Fix inconsistency in accessing PC/nextPC, which also clarifies which handlers return nextPC values as opposed to setting them.
Diffstat (limited to 'model/riscv_insts_next.sail')
| -rw-r--r-- | model/riscv_insts_next.sail | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/model/riscv_insts_next.sail b/model/riscv_insts_next.sail index 926a3b5..7b87826 100644 --- a/model/riscv_insts_next.sail +++ b/model/riscv_insts_next.sail @@ -9,7 +9,7 @@ mapping clause encdec = URET() function clause execute URET() = { if (~ (haveUsrMode())) then handle_illegal() - else nextPC = handle_exception(cur_privilege, CTL_URET(), PC); + else set_next_pc(exception_handler(cur_privilege, CTL_URET(), PC)); false } |