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| author | Thomas Bauereiss <tb592@cl.cam.ac.uk> | 2019-10-04 17:08:25 +0100 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-10-09 21:40:05 -0700 |
| commit | a13c0a435804a9a8250054c2e9af2eacfa883164 (patch) | |
| tree | 213a030c3ca2b950f3d691c2932185fea48ee92d /model/riscv_fetch.sail | |
| parent | ba18f0f59cee8e3c32cfaa980c0d109399284844 (diff) | |
| download | sail-riscv-a13c0a435804a9a8250054c2e9af2eacfa883164.zip sail-riscv-a13c0a435804a9a8250054c2e9af2eacfa883164.tar.gz sail-riscv-a13c0a435804a9a8250054c2e9af2eacfa883164.tar.bz2 | |
Read/write memory values and metadata together atomically
For Lem, bypass the Sail implementation of {read,write}_ram and map to
atomic primitives directly.
We might want to make these functions primitive for other backends as well.
Diffstat (limited to 'model/riscv_fetch.sail')
| -rw-r--r-- | model/riscv_fetch.sail | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/model/riscv_fetch.sail b/model/riscv_fetch.sail index 64aff4b..d091756 100644 --- a/model/riscv_fetch.sail +++ b/model/riscv_fetch.sail @@ -4,7 +4,7 @@ function isRVC(h : half) -> bool = ~ (h[1 .. 0] == 0b11) -val fetch : unit -> FetchResult effect {escape, rmem, rreg, wmv, wmvt, wreg} +val fetch : unit -> FetchResult effect {escape, rmem, rmemt, rreg, wmv, wmvt, wreg} function fetch() -> FetchResult = /* fetch PC check for extensions: extensions return a transformed PC to fetch, * but any exceptions use the untransformed PC. |