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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2020-02-12 09:24:11 -0800 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2020-02-12 09:24:11 -0800 |
| commit | 83df28ae4128babc55157756b63f8684e94e55ca (patch) | |
| tree | d8e92236c389bb0c26576a1865ba3997babd5016 /model/riscv_duopod.sail | |
| parent | c34a5ce3e05624eff9daa89770e5d6be627393a4 (diff) | |
| parent | ca57c1be19447a5ec831292f0ca4081ffc13b436 (diff) | |
| download | sail-riscv-83df28ae4128babc55157756b63f8684e94e55ca.zip sail-riscv-83df28ae4128babc55157756b63f8684e94e55ca.tar.gz sail-riscv-83df28ae4128babc55157756b63f8684e94e55ca.tar.bz2 | |
Merge branch 'master' into gdbgdb
Diffstat (limited to 'model/riscv_duopod.sail')
| -rw-r--r-- | model/riscv_duopod.sail | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/model/riscv_duopod.sail b/model/riscv_duopod.sail index 395a332..b811824 100644 --- a/model/riscv_duopod.sail +++ b/model/riscv_duopod.sail @@ -1,4 +1,6 @@ -// This file depends on the xlen definitions in riscv_xlen.sail. + +$include "prelude.sail" +$include "riscv_xlen64.sail" type regbits = bits(5) @@ -23,7 +25,7 @@ function rX(r) = val wX : (regbits, xlenbits) -> unit effect {wreg} -function wX (r, v) = +function wX(r, v) = if r != 0b00000 then { Xs[unsigned(r)] = v; } |