Update docs for previous commits.

2 files changed, 12 insertions, 5 deletions

diff --git a/doc/ExtendingGuide.md b/doc/ExtendingGuide.md
index f38130a..4533b8b 100644
--- a/doc/ExtendingGuide.md
+++ b/doc/ExtendingGuide.md
@@ -103,6 +103,13 @@ examples on how this can done.  These instruction definitions can
 access any newly defined architectural state and perform virtual or
 physical memory accesses as is done in `riscv.sail`.
 
+Interposing on instruction decode
+---------------------------------
+
+An extension may wish to check and transform a decoded instruction.
+This is supported via a post-decode extension hook, the default
+implementation of which is provided in `riscv_decode_ext.sail`.
+
 General guidelines
 ------------------
 
diff --git a/doc/ReadingGuide.md b/doc/ReadingGuide.md
index 9145ac9..5c7e656 100644
--- a/doc/ReadingGuide.md
+++ b/doc/ReadingGuide.md
@@ -90,11 +90,11 @@ The model contains the following Sail modules in the `model` directory:
 - `riscv_step.sail` implements the top-level fetch and execute loop.
   The `fetch` is done in 16-bit granules to handle RVC instructions.
   The `step` function performs the instruction fetch, handles any
-  fetch errors, dispatches the execution of each instruction, and
-  checks for any pending interrupts that may need to be handled.  A
-  `loop` function implements the execute loop, and uses the same HTIF
-  (host-target interface) mechanism as the Spike emulator to detect
-  termination of execution.
+  fetch errors, decodes the fetched value, dispatches the execution of
+  the decoded instruction, and checks for any pending interrupts that may
+  need to be handled.  A `loop` function implements the execute loop,
+  and uses the same HTIF (host-target interface) mechanism as the
+  Spike emulator to detect termination of execution.
 
 - `riscv_analysis.sail` is used in the formal operational RVWMO memory
   model.