doc: tweaks.

2 files changed, 12 insertions, 11 deletions

diff --git a/doc/ExtendingGuide.md b/doc/ExtendingGuide.md
index c3cee02..d128ebd 100644
--- a/doc/ExtendingGuide.md
+++ b/doc/ExtendingGuide.md
@@ -13,11 +13,12 @@ privilege level (such as hypervisor-mode registers), additional access
 control checks would need to be provided as is done for the standard
 CSRs in `riscv_sys.sail`.
 
-Adding a new privilege level will normally be accompanied by defining
-new exception causes and their encodings.  This will require modifying
-and extending the existing definitions for privilege levels and
-exceptions in `riscv_types.sail`, and modifying the exception handling
-and privilege transition functions in `riscv_sys.sail`.
+Adding a new privilege level or functionality restricted by privilege
+level will normally be accompanied by defining new exception causes
+and their encodings.  This will require modifying and extending the
+existing definitions for privilege levels and exceptions in
+`riscv_types.sail`, and modifying the exception handling and privilege
+transition functions in `riscv_sys.sail`.
 
 Adding low-level platform functionality
 ---------------------------------------
@@ -28,14 +29,14 @@ purview of the formal model itself, and typically is not done
 directly in the Sail model.  However, bindings to this external
 functionality can be provided to Sail definitions using the `extern`
 construct of the Sail language. `riscv_platform.sail` can be examined
-for how this is done for the SiFive core-local interrupt (CLINT)
-controller, and the HTIF timer and terminal devices.  The
+to see how this is done for the SiFive core-local interrupt (CLINT)
+controller, the HTIF timer and terminal devices.  The
 implementation of the actual functionality provided by these MMIO
 devices would need to be added to the C and OCaml emulators.
 
 If this functionality requires the definition of new interrupt
 sources, their encodings would need to be added to `riscv_types.sail`,
-and their delegation and handling to `riscv_sys.sail`.
+and their delegation and handling added to `riscv_sys.sail`.
 
 Interposing on memory access
 ----------------------------
@@ -53,7 +54,7 @@ physical memory access is implemented in `riscv_mem.sail` with helpers
 in `prelude.sail`.
 
 Virtual memory is implemented in `riscv_vmem.sail`, and defining new
-address translation schemes or will require updating modifying the
+address translation schemes will require updating modifying the
 top-level `translateAddr` function.  Any access control checks on
 virtual addresses and the specifics of the address translation can be
 specified in a separate file.  This functionality can access any newly
diff --git a/doc/ReadingGuide.md b/doc/ReadingGuide.md
index d60186e..1e851de 100644
--- a/doc/ReadingGuide.md
+++ b/doc/ReadingGuide.md
@@ -9,12 +9,12 @@ The model contains the following Sail modules in the `model` directory:
 
 - `prelude.sail` contains useful Sail library functions.  This file
   should be referred to as needed.  The lowest level memory access
-  primitives are defined in this file, and are typically implemented
+  primitives are defined in this file, and are implemented
   by the various Sail backends.
 
 - `riscv_types.sail` contains some basic RISC-V definitions.  This
   file should be read first, since it provides basic definitions that
-  are pervasively used throughout the specification, such as privilege
+  are used throughout the specification, such as privilege
   levels, registers and register access, interrupt and exception
   definitions and numbering, and types used to define memory accesses.