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author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-02-20 12:35:20 -0800 |
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committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-02-20 13:04:26 -0800 |
commit | 844feb92ca50901c79fbdd05a0e808d335207ae1 (patch) | |
tree | aff4ae3b6ed3a627d1f321743165d9fc8ecf3d96 /c_emulator | |
parent | 6a4eb9211bab5070dc55cea9046e1ffc4e20eafc (diff) | |
download | sail-riscv-844feb92ca50901c79fbdd05a0e808d335207ae1.zip sail-riscv-844feb92ca50901c79fbdd05a0e808d335207ae1.tar.gz sail-riscv-844feb92ca50901c79fbdd05a0e808d335207ae1.tar.bz2 |
Add ELF architecture checks to the loaders in the OCaml and C emulators.
Diffstat (limited to 'c_emulator')
-rw-r--r-- | c_emulator/riscv_sail.h | 1 | ||||
-rw-r--r-- | c_emulator/riscv_sim.c | 31 |
2 files changed, 27 insertions, 5 deletions
diff --git a/c_emulator/riscv_sail.h b/c_emulator/riscv_sail.h index 424b64b..721f180 100644 --- a/c_emulator/riscv_sail.h +++ b/c_emulator/riscv_sail.h @@ -28,6 +28,7 @@ unit zrvfi_halt_exec_packet(unit); void zrvfi_get_exec_packet(sail_bits *rop, unit); #endif +extern mach_bits zxlen_val; extern bool zhtif_done; extern mach_bits zhtif_exit_code; extern bool have_exception; diff --git a/c_emulator/riscv_sim.c b/c_emulator/riscv_sim.c index 2a70167..9cca587 100644 --- a/c_emulator/riscv_sim.c +++ b/c_emulator/riscv_sim.c @@ -24,6 +24,9 @@ struct tv_spike_t; #endif +const char *RV64ISA = "RV64IMAC"; +const char *RV32ISA = "RV32IMAC"; + /* Selected CSRs from riscv-isa-sim/riscv/encoding.h */ #define CSR_STVEC 0x105 #define CSR_SEPC 0x141 @@ -216,15 +219,26 @@ char *process_args(int argc, char **argv) return argv[optind]; } +void check_elf(bool is32bit) +{ + if (is32bit) { + if (zxlen_val != 32) { + fprintf(stderr, "32-bit ELF not supported by RV%lu model.\n", zxlen_val); + exit(1); + } + } else { + if (zxlen_val != 64) { + fprintf(stderr, "64-bit ELF not supported by RV%lu model.\n", zxlen_val); + exit(1); + } + } +} uint64_t load_sail(char *f) { bool is32bit; uint64_t entry; load_elf(f, &is32bit, &entry); - if (is32bit) { - fprintf(stderr, "32-bit RISC-V not yet supported.\n"); - exit(1); - } + check_elf(is32bit); fprintf(stdout, "ELF Entry @ %lx\n", entry); /* locate htif ports */ if (lookup_sym(f, "tohost", &rv_htif_tohost) < 0) { @@ -356,9 +370,13 @@ void init_sail_reset_vector(uint64_t entry) zPC = rv_rom_base; } -void init_sail(uint64_t elf_entry) +void preinit_sail() { model_init(); +} + +void init_sail(uint64_t elf_entry) +{ zinit_platform(UNIT); zinit_sys(UNIT); #ifdef RVFI_DII @@ -648,6 +666,9 @@ int main(int argc, char **argv) char *file = process_args(argc, argv); init_logs(); + // Initialize model so that we can check its architecture. + preinit_sail(); + if (gettimeofday(&init_start, NULL) < 0) { fprintf(stderr, "Cannot gettimeofday: %s\n", strerror(errno)); exit(1); |