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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-03-07 12:48:58 -0800 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-03-07 14:48:57 -0800 |
| commit | 1d85b196527dfeb1e126364afeaa5b7e632cc2a9 (patch) | |
| tree | bf91691b93f87298f2e41cd908956027396f8946 /README.md | |
| parent | 7e6961b52183158d8d22344fa509b03253e04463 (diff) | |
| download | sail-riscv-1d85b196527dfeb1e126364afeaa5b7e632cc2a9.zip sail-riscv-1d85b196527dfeb1e126364afeaa5b7e632cc2a9.tar.gz sail-riscv-1d85b196527dfeb1e126364afeaa5b7e632cc2a9.tar.bz2 | |
Fix docs about sel4 boot.
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 6 |
1 files changed, 3 insertions, 3 deletions
@@ -123,9 +123,9 @@ simulator is available from `./ocaml_emulator/riscv_ocaml_sim_<arch> -h` and `./c_emulator/riscv_sim_<arch> -h`. Some useful options are: configuring whether misaligned accesses trap -(--enable-misaligned for C and -enable-misaligned for OCaml), and -whether page-table walks update PTE bits (--enable-dirty-update for C -and -enable-dirty-update for OCaml). +(`--enable-misaligned` for C and `-enable-misaligned` for OCaml), and +whether page-table walks update PTE bits (`--enable-dirty-update` for C +and `-enable-dirty-update` for OCaml). Booting OS images ----------------- |