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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2018-11-30 12:13:09 -0800 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2018-11-30 12:14:49 -0800 |
| commit | 427c25e2fb8a2dd1b24f11762f5dd9a4585a1f92 (patch) | |
| tree | f16c63a0aa4a3ad064215a12dd8453d0d0dbedf9 /README.md | |
| parent | 5b8a0227caf7b83c5d60d3ddeb613b5b77d23f7c (diff) | |
| download | sail-riscv-427c25e2fb8a2dd1b24f11762f5dd9a4585a1f92.zip sail-riscv-427c25e2fb8a2dd1b24f11762f5dd9a4585a1f92.tar.gz sail-riscv-427c25e2fb8a2dd1b24f11762f5dd9a4585a1f92.tar.bz2 | |
Add some caveats for OS boot.
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 12 |
1 files changed, 12 insertions, 0 deletions
@@ -102,3 +102,15 @@ spike --dump-dts . | dtc > spike.dtb (The '.' above is to workaround a minor Spike bug and may not be needed in future Spike versions.) + +Caveats for OS boot +------------------- + +- Some OS toolchains generate obsolete LR/SC instructions with now + illegal combinations of `.aq` and `.rl` flags. You can work-around + this by changing `riscv_mem.sail` to accept these flags. + +- One needs to manually ensure that the DTB used for the C model + accurately describes the physical memory map implemented in the C + platform. This will not be needed once the C model can generate its + own DTB. |