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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-03-07 11:00:52 -0800 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-03-07 11:00:52 -0800 |
| commit | 7459f38006072df3f31483ebe4ea2a08f0597049 (patch) | |
| tree | 66991c7012914c1f030e122642d340d0e4d8ba21 /README.md | |
| parent | 8bb8f1cc56ad766f888eaf73b827694e8cff3603 (diff) | |
| download | sail-riscv-7459f38006072df3f31483ebe4ea2a08f0597049.zip sail-riscv-7459f38006072df3f31483ebe4ea2a08f0597049.tar.gz sail-riscv-7459f38006072df3f31483ebe4ea2a08f0597049.tar.bz2 | |
More doc tweaks.
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 6 |
1 files changed, 6 insertions, 0 deletions
@@ -110,6 +110,9 @@ A suite of RV32 and RV64 test programs derived from the included under [test/riscv-tests/](test/riscv-tests/). The test-suite can be run using `test/run_tests.sh`. +Configuring platform options +---------------------------- + Some information on additional configuration options for each simulator is available from `./ocaml_emulator/riscv_ocaml_sim_<arch> -h` and `./c_emulator/riscv_sim_<arch> -h`. @@ -119,5 +122,8 @@ Some useful options are: configuring whether misaligned accesses trap whether page-table walks update PTE bits (--enable-dirty-update for C and -enable-dirty-update for OCaml). +Booting OS images +----------------- + For booting operating system images, see the information under the [os-boot/](os-boot/) subdirectory. |