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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2020-04-02 17:00:19 -0700 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2020-04-02 17:01:15 -0700 |
| commit | f9a480bbf0c2584defb1d743a6403fe30ddf3b93 (patch) | |
| tree | b155a475e1940cb1c015cb9a46a9533bd3daaf7d /Makefile | |
| parent | 0403086181fc303d54c85b700ab917554effbcdb (diff) | |
| download | sail-riscv-f9a480bbf0c2584defb1d743a6403fe30ddf3b93.zip sail-riscv-f9a480bbf0c2584defb1d743a6403fe30ddf3b93.tar.gz sail-riscv-f9a480bbf0c2584defb1d743a6403fe30ddf3b93.tar.bz2 | |
Fix a bug in the softfloat interface that caused exception flags not to get accrued into fcsr.
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -21,7 +21,7 @@ endif # Instruction sources, depending on target SAIL_CHECK_SRCS = riscv_addr_checks_common.sail riscv_addr_checks.sail riscv_misa_ext.sail SAIL_DEFAULT_INST = riscv_insts_base.sail riscv_insts_aext.sail riscv_insts_cext.sail riscv_insts_mext.sail riscv_insts_zicsr.sail riscv_insts_next.sail -SAIL_DEFAULT_INST += riscv_softfloat_interface.sail riscv_insts_fext.sail +SAIL_DEFAULT_INST += riscv_insts_fext.sail ifeq ($(ARCH),RV64) SAIL_DEFAULT_INST +=riscv_insts_dext.sail endif @@ -38,7 +38,7 @@ SAIL_SYS_SRCS += riscv_next_regs.sail SAIL_SYS_SRCS += riscv_sys_exceptions.sail # default basic helpers for exception handling SAIL_SYS_SRCS += riscv_sync_exception.sail # define the exception structure used in the model SAIL_SYS_SRCS += riscv_next_control.sail # helpers for the 'N' extension -SAIL_SYS_SRCS += riscv_fdext_regs.sail riscv_fdext_control.sail +SAIL_SYS_SRCS += riscv_softfloat_interface.sail riscv_fdext_regs.sail riscv_fdext_control.sail SAIL_SYS_SRCS += riscv_csr_ext.sail # access to CSR extensions SAIL_SYS_SRCS += riscv_sys_control.sail # general exception handling |