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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2020-09-04 15:24:27 -0700 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2020-09-04 15:27:25 -0700 |
| commit | c138a086f91552bc158f3bfab9a52221a0819171 (patch) | |
| tree | 9d38baa4c1d92b69b0041fb7116d8bf872f10b46 /Makefile | |
| parent | 33987151f57b401bc7d71594f02d5abbfadb2e78 (diff) | |
| download | sail-riscv-c138a086f91552bc158f3bfab9a52221a0819171.zip sail-riscv-c138a086f91552bc158f3bfab9a52221a0819171.tar.gz sail-riscv-c138a086f91552bc158f3bfab9a52221a0819171.tar.bz2 | |
Handle hints explicitly in order to not trap on them.
This currently maps their assembly renditions to non-standard instructions to preserve bidirectional mappings.
Fixes #67 and #29.
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -20,7 +20,7 @@ endif # Instruction sources, depending on target SAIL_CHECK_SRCS = riscv_addr_checks_common.sail riscv_addr_checks.sail riscv_misa_ext.sail -SAIL_DEFAULT_INST = riscv_insts_base.sail riscv_insts_aext.sail riscv_insts_cext.sail riscv_insts_mext.sail riscv_insts_zicsr.sail riscv_insts_next.sail +SAIL_DEFAULT_INST = riscv_insts_base.sail riscv_insts_aext.sail riscv_insts_cext.sail riscv_insts_mext.sail riscv_insts_zicsr.sail riscv_insts_next.sail riscv_insts_hints.sail SAIL_DEFAULT_INST += riscv_insts_fext.sail riscv_insts_cfext.sail ifeq ($(ARCH),RV64) SAIL_DEFAULT_INST += riscv_insts_dext.sail riscv_insts_cdext.sail |