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| author | Robert Norton <rmn30@cam.ac.uk> | 2019-09-16 17:50:25 +0100 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-09-18 09:42:12 -0700 |
| commit | 8c418a0255f51bf2f9283de6117f8c34630b018b (patch) | |
| tree | 7039b5e36917f9039451c669e21afa7e78d79906 /Makefile | |
| parent | c54a10dc0d45f8946d3d4a127c358bc8e9f2e914 (diff) | |
| download | sail-riscv-8c418a0255f51bf2f9283de6117f8c34630b018b.zip sail-riscv-8c418a0255f51bf2f9283de6117f8c34630b018b.tar.gz sail-riscv-8c418a0255f51bf2f9283de6117f8c34630b018b.tar.bz2 | |
Add a hook for extensions to supress writes to misa.C if necessary.
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -16,7 +16,7 @@ else endif # Instruction sources, depending on target -SAIL_CHECK_SRCS = riscv_addr_checks_common.sail riscv_addr_checks.sail +SAIL_CHECK_SRCS = riscv_addr_checks_common.sail riscv_addr_checks.sail riscv_misa_ext.sail SAIL_DEFAULT_INST = riscv_insts_base.sail riscv_insts_aext.sail riscv_insts_cext.sail riscv_insts_mext.sail riscv_insts_zicsr.sail riscv_insts_next.sail SAIL_SEQ_INST = $(SAIL_DEFAULT_INST) riscv_jalr_seq.sail SAIL_RMEM_INST = $(SAIL_DEFAULT_INST) riscv_jalr_rmem.sail riscv_insts_rmem.sail |