Add Zfa extension support (excl. quad-precision)

This commit adds the following:
- infrastructure for Zfa (e.g., existence macro)
- support for the following instructions:
  + FLI.[HSD]
  + FMINM.[HSD] and FMAXM.[HSD]
  + FROUND.[HSD] and FROUNDNX.[HSD]
  + FMVH.X.D and FMVP.D.X
  + FLEQ.[HSD] and FLTQ.[HSD]
  + FCVTMOD.W.D

Note the following implementation details:

FMINM and FMAXM provide similar functionality to FMIN and FMAX,
differing only in their NaN-handling:
 * FMIN/FMAX return a canonical NaN only if both operands are a NaN
 * FMINM/FMAXM return a canonical Nan if any operand is a NaN
Consequently, the implementation is identical to FMIN/FMAX with only
the NaN-related tests changed.

FROUND instruction rounds a floating-point number in floating-point
register rs1 and writes that integer, represented as a floating-point
number to floating-point register rd while:
* Zero and infinite inputs are copied to rd unmodified.
* NaN inputs cause the invalid operation exception flag to be set.
FROUNDNX instruction is defined similarly, but also sets the inexact
exception flag if the input differs from the rounded result and is not
NaN.

FMVH.X.D instruction is available for RV32 only and moves bits 63:32
of floating-point register rs1 into integer register rd.

FMVP.D.X instruction is available for RV32 only and moves a
double-precision number from a pair of integer registers into a
floating-point register. Integer registers rs1 and rs2 supply bits
31:0 and 63:32, respectively.

FLEQ and FLTQ instructions are defined like the FLE and FLT
instructions, except that quiet NaN inputs do not cause the invalid
operation exception flag to be set.

The FCVTMOD.W.D instruction is defined similarly to the FCVT.W.D
instruction, with the following differences:
 * FCVTMOD.W.D always rounds towards zero.
 * Bits 31:0 are taken from the rounded, unbounded two's complement
   result, then sign-extended to XLEN bits and written to integer
   register rd.
 * Positive infinity, negative infinity and NaN are converted to zero.

Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu>
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>

1 files changed, 3 insertions, 0 deletions

diff --git a/Makefile b/Makefile
index 5365f04..17b8a0a 100644
--- a/Makefile
+++ b/Makefile
@@ -29,6 +29,9 @@ SAIL_DEFAULT_INST += riscv_insts_zbc.sail
 SAIL_DEFAULT_INST += riscv_insts_zbs.sail
 
 SAIL_DEFAULT_INST += riscv_insts_zfh.sail
+# Zfa needs to be added after fext, dext and Zfh (as it needs
+# definitions from those)
+SAIL_DEFAULT_INST += riscv_insts_zfa.sail
 
 SAIL_DEFAULT_INST += riscv_insts_zkn.sail
 SAIL_DEFAULT_INST += riscv_insts_zks.sail