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| author | Alasdair <alasdair.armstrong@gmail.com> | 2019-06-06 19:47:04 +0100 |
|---|---|---|
| committer | Alasdair <alasdair.armstrong@gmail.com> | 2019-06-06 19:47:04 +0100 |
| commit | 6019eb69020cb87216ec1889eb82be7443fa1fb3 (patch) | |
| tree | f8780cc30572e32b05844ad8c5824cdfdda25bbd /Makefile | |
| parent | d0dfe4c7a0c12ec10dd7b4c663f8f47166e0f900 (diff) | |
| download | sail-riscv-6019eb69020cb87216ec1889eb82be7443fa1fb3.zip sail-riscv-6019eb69020cb87216ec1889eb82be7443fa1fb3.tar.gz sail-riscv-6019eb69020cb87216ec1889eb82be7443fa1fb3.tar.bz2 | |
Add a makefile target to pre-compile the model for axiomatic concurrency tool
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 3 |
1 files changed, 3 insertions, 0 deletions
@@ -144,6 +144,9 @@ check: $(SAIL_SRCS) model/main.sail Makefile interpret: $(SAIL_SRCS) model/main.sail $(SAIL) -i $(SAIL_FLAGS) $(SAIL_SRCS) model/main.sail +riscv.smt_model: $(SAIL_SRCS) + $(SAIL) -smt_serialize $(SAIL_FLAGS) $(SAIL_SRCS) -o riscv + cgen: $(SAIL_SRCS) model/main.sail $(SAIL) -cgen $(SAIL_FLAGS) $(SAIL_SRCS) model/main.sail |