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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-07-15 11:07:56 -0700 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-07-15 11:18:44 -0700 |
| commit | 39ed62d79e9f4ead6f52e755df9f9562e44696ac (patch) | |
| tree | 4b4ac003bdbf86f3b01d68667c47f464f93a87ae /Makefile | |
| parent | 8b39adca2fafad9037f21202782ac29c776b7526 (diff) | |
| download | sail-riscv-39ed62d79e9f4ead6f52e755df9f9562e44696ac.zip sail-riscv-39ed62d79e9f4ead6f52e755df9f9562e44696ac.tar.gz sail-riscv-39ed62d79e9f4ead6f52e755df9f9562e44696ac.tar.bz2 | |
Allow extensions to types of memory access, and factor out PTE and PTW definitions.
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -36,7 +36,7 @@ SAIL_SYS_SRCS += riscv_sys_control.sail # general exception handling SAIL_RV32_VM_SRCS = riscv_vmem_sv32.sail riscv_vmem_rv32.sail SAIL_RV64_VM_SRCS = riscv_vmem_sv39.sail riscv_vmem_sv48.sail riscv_vmem_rv64.sail -SAIL_VM_SRCS = riscv_vmem_common.sail riscv_vmem_tlb.sail +SAIL_VM_SRCS = riscv_pte.sail riscv_ptw.sail riscv_vmem_common.sail riscv_vmem_tlb.sail ifeq ($(ARCH),RV32) SAIL_VM_SRCS += $(SAIL_RV32_VM_SRCS) else @@ -50,7 +50,7 @@ SAIL_REGS_SRCS = riscv_reg_type.sail riscv_regs.sail riscv_pc_access.sail riscv_ SAIL_REGS_SRCS += riscv_pmp_regs.sail riscv_pmp_control.sail SAIL_REGS_SRCS += riscv_ext_regs.sail $(SAIL_CHECK_SRCS) -SAIL_ARCH_SRCS = $(PRELUDE) riscv_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail +SAIL_ARCH_SRCS = $(PRELUDE) riscv_types.sail riscv_vmem_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail SAIL_ARCH_SRCS += riscv_mem.sail $(SAIL_VM_SRCS) SAIL_ARCH_RVFI_SRCS = $(PRELUDE) rvfi_dii.sail riscv_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail riscv_mem.sail $(SAIL_VM_SRCS) SAIL_STEP_SRCS = riscv_step_common.sail riscv_step_ext.sail riscv_decode_ext.sail riscv_fetch.sail riscv_step.sail |