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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-02-12 18:11:34 -0800 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-02-12 18:51:53 -0800 |
| commit | 82e1ad350fb49deedb7ac9d79a45bc6185844f78 (patch) | |
| tree | 681af0c21e27cfa03561dfabbc886554fb972aaf /Makefile | |
| parent | b860868ed7bc762f31d29aaea50873e596db6861 (diff) | |
| download | sail-riscv-82e1ad350fb49deedb7ac9d79a45bc6185844f78.zip sail-riscv-82e1ad350fb49deedb7ac9d79a45bc6185844f78.tar.gz sail-riscv-82e1ad350fb49deedb7ac9d79a45bc6185844f78.tar.bz2 | |
Start extracting bits of vmem that should be common to RV32, and add some definitions for Sv32 and Sv48.
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 6 |
1 files changed, 4 insertions, 2 deletions
@@ -7,10 +7,12 @@ SAIL_RMEM_INST_SRCS = riscv_insts_begin.sail $(SAIL_RMEM_INST) riscv_insts_end.s SAIL_SYS_SRCS = riscv_csr_map.sail riscv_sys_regs.sail riscv_next_regs.sail riscv_next_control.sail riscv_sys_control.sail +SAIL_VM_SRCS = riscv_vmem_common.sail riscv_vmem.sail + # non-instruction sources PRELUDE = prelude.sail prelude_mapping.sail riscv_xlen.sail prelude_mem.sail -SAIL_OTHER_SRCS = $(PRELUDE) riscv_types.sail $(SAIL_SYS_SRCS) riscv_platform.sail riscv_mem.sail riscv_vmem.sail -SAIL_OTHER_RVFI_SRCS = $(PRELUDE) rvfi_dii.sail riscv_types.sail $(SAIL_SYS_SRCS) riscv_platform.sail riscv_mem.sail riscv_vmem.sail +SAIL_OTHER_SRCS = $(PRELUDE) riscv_types.sail $(SAIL_SYS_SRCS) riscv_platform.sail riscv_mem.sail $(SAIL_VM_SRCS) +SAIL_OTHER_RVFI_SRCS = $(PRELUDE) rvfi_dii.sail riscv_types.sail $(SAIL_SYS_SRCS) riscv_platform.sail riscv_mem.sail $(SAIL_VM_SRCS) PRELUDE_SRCS = $(addprefix model/,$(PRELUDE)) SAIL_SRCS = $(addprefix model/,$(SAIL_OTHER_SRCS) $(SAIL_SEQ_INST_SRCS) riscv_step.sail riscv_analysis.sail) |