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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2020-04-27 23:18:21 -0700 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2020-04-27 23:18:21 -0700 |
| commit | b46497ddced0256cc263ce2de44c5c8bfc0fe6eb (patch) | |
| tree | 083c940338954b03ffad15ea734351c024fde855 | |
| parent | 8e6281866d063f32b1b728c8933ffdb8e45cd030 (diff) | |
| download | sail-riscv-b46497ddced0256cc263ce2de44c5c8bfc0fe6eb.zip sail-riscv-b46497ddced0256cc263ce2de44c5c8bfc0fe6eb.tar.gz sail-riscv-b46497ddced0256cc263ce2de44c5c8bfc0fe6eb.tar.bz2 | |
Add the mcountinhibit register.
| -rw-r--r-- | model/riscv_insts_zicsr.sail | 3 | ||||
| -rw-r--r-- | model/riscv_platform.sail | 4 | ||||
| -rw-r--r-- | model/riscv_sys_regs.sail | 13 |
3 files changed, 19 insertions, 1 deletions
diff --git a/model/riscv_insts_zicsr.sail b/model/riscv_insts_zicsr.sail index d2518cd..c778b8f 100644 --- a/model/riscv_insts_zicsr.sail +++ b/model/riscv_insts_zicsr.sail @@ -28,6 +28,8 @@ function readCSR csr : csreg -> xlenbits = { (0x304, _) => mie.bits(), (0x305, _) => get_mtvec(), (0x306, _) => EXTZ(mcounteren.bits()), + (0x320, _) => EXTZ(mcountinhibit.bits()), + (0x340, _) => mscratch, (0x341, _) => get_xret_target(Machine) & pc_alignment_mask(), (0x342, _) => mcause.bits(), @@ -110,6 +112,7 @@ function writeCSR (csr : csreg, value : xlenbits) -> unit = { (0x304, _) => { mie = legalize_mie(mie, value); Some(mie.bits()) }, (0x305, _) => { Some(set_mtvec(value)) }, (0x306, _) => { mcounteren = legalize_mcounteren(mcounteren, value); Some(EXTZ(mcounteren.bits())) }, + (0x320, _) => { mcountinhibit = legalize_mcountinhibit(mcountinhibit, value); Some(EXTZ(mcountinhibit.bits())) }, (0x340, _) => { mscratch = value; Some(mscratch) }, (0x341, _) => { Some(set_xret_target(Machine, value)) }, (0x342, _) => { mcause->bits() = value; Some(mcause.bits()) }, diff --git a/model/riscv_platform.sail b/model/riscv_platform.sail index 7e07cf1..01f7b4f 100644 --- a/model/riscv_platform.sail +++ b/model/riscv_platform.sail @@ -250,7 +250,9 @@ function clint_store(addr, width, data) = { val tick_clock : unit -> unit effect {rreg, wreg} function tick_clock() = { - mcycle = mcycle + 1; + if mcountinhibit.CY() == 0b0 + then mcycle = mcycle + 1; + mtime = mtime + 1; clint_dispatch() } diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail index e783472..cae7ccb 100644 --- a/model/riscv_sys_regs.sail +++ b/model/riscv_sys_regs.sail @@ -398,6 +398,19 @@ function legalize_scounteren(c : Counteren, v : xlenbits) -> Counteren = { c } +bitfield Counterin : bits(32) = { + /* no HPM counters yet */ + IR : 2, + CY : 0 +} +register mcountinhibit : Counterin + +function legalize_mcountinhibit(c : Counterin, v : xlenbits) -> Counterin = { + let c = update_IR(c, [v[2]]); + let c = update_CY(c, [v[0]]); + c +} + register mcycle : bits(64) register mtime : bits(64) |