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author | Shaked Flur <sflur@google.com> | 2022-01-19 14:01:19 +0000 |
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committer | Shaked Flur <sflur@google.com> | 2022-01-19 14:01:19 +0000 |
commit | 8d93d9717ada0f58438dbf1be843f19f9e44e2ef (patch) | |
tree | d341c60e8e7a4834fd1a82ebbdba4d294fd95e18 | |
parent | 3026c56e7c2ec5e33a4e9f7e54323b9f8ad6f3aa (diff) | |
download | sail-riscv-8d93d9717ada0f58438dbf1be843f19f9e44e2ef.zip sail-riscv-8d93d9717ada0f58438dbf1be843f19f9e44e2ef.tar.gz sail-riscv-8d93d9717ada0f58438dbf1be843f19f9e44e2ef.tar.bz2 |
Change GPR names to x<n> (e.g. x1), instead of the abi namesx_regs
-rw-r--r-- | model/riscv_regs.sail | 144 |
1 files changed, 72 insertions, 72 deletions
diff --git a/model/riscv_regs.sail b/model/riscv_regs.sail index 4b4a1ea..6ef09e0 100644 --- a/model/riscv_regs.sail +++ b/model/riscv_regs.sail @@ -153,38 +153,38 @@ val reg_name_abi : regidx -> string function reg_name_abi(r) = { match (r) { - 0b00000 => "zero", - 0b00001 => "ra", - 0b00010 => "sp", - 0b00011 => "gp", - 0b00100 => "tp", - 0b00101 => "t0", - 0b00110 => "t1", - 0b00111 => "t2", - 0b01000 => "fp", - 0b01001 => "s1", - 0b01010 => "a0", - 0b01011 => "a1", - 0b01100 => "a2", - 0b01101 => "a3", - 0b01110 => "a4", - 0b01111 => "a5", - 0b10000 => "a6", - 0b10001 => "a7", - 0b10010 => "s2", - 0b10011 => "s3", - 0b10100 => "s4", - 0b10101 => "s5", - 0b10110 => "s6", - 0b10111 => "s7", - 0b11000 => "s8", - 0b11001 => "s9", - 0b11010 => "s10", - 0b11011 => "s11", - 0b11100 => "t3", - 0b11101 => "t4", - 0b11110 => "t5", - 0b11111 => "t6" + 0b00000 => "x0", + 0b00001 => "x1", + 0b00010 => "x2", + 0b00011 => "x3", + 0b00100 => "x4", + 0b00101 => "x5", + 0b00110 => "x6", + 0b00111 => "x7", + 0b01000 => "x8", + 0b01001 => "x9", + 0b01010 => "x10", + 0b01011 => "x11", + 0b01100 => "x12", + 0b01101 => "x13", + 0b01110 => "x14", + 0b01111 => "x15", + 0b10000 => "x16", + 0b10001 => "x17", + 0b10010 => "x18", + 0b10011 => "x19", + 0b10100 => "x20", + 0b10101 => "x21", + 0b10110 => "x22", + 0b10111 => "x23", + 0b11000 => "x24", + 0b11001 => "x25", + 0b11010 => "x26", + 0b11011 => "x27", + 0b11100 => "x28", + 0b11101 => "x29", + 0b11110 => "x30", + 0b11111 => "x31" } } @@ -194,49 +194,49 @@ overload to_str = {reg_name_abi} val reg_name : bits(5) <-> string mapping reg_name = { - 0b00000 <-> "zero", - 0b00001 <-> "ra", - 0b00010 <-> "sp", - 0b00011 <-> "gp", - 0b00100 <-> "tp", - 0b00101 <-> "t0", - 0b00110 <-> "t1", - 0b00111 <-> "t2", - 0b01000 <-> "fp", - 0b01001 <-> "s1", - 0b01010 <-> "a0", - 0b01011 <-> "a1", - 0b01100 <-> "a2", - 0b01101 <-> "a3", - 0b01110 <-> "a4", - 0b01111 <-> "a5", - 0b10000 <-> "a6", - 0b10001 <-> "a7", - 0b10010 <-> "s2", - 0b10011 <-> "s3", - 0b10100 <-> "s4", - 0b10101 <-> "s5", - 0b10110 <-> "s6", - 0b10111 <-> "s7", - 0b11000 <-> "s8", - 0b11001 <-> "s9", - 0b11010 <-> "s10", - 0b11011 <-> "s11", - 0b11100 <-> "t3", - 0b11101 <-> "t4", - 0b11110 <-> "t5", - 0b11111 <-> "t6" + 0b00000 <-> "x0", + 0b00001 <-> "x1", + 0b00010 <-> "x2", + 0b00011 <-> "x3", + 0b00100 <-> "x4", + 0b00101 <-> "x5", + 0b00110 <-> "x6", + 0b00111 <-> "x7", + 0b01000 <-> "x8", + 0b01001 <-> "x9", + 0b01010 <-> "x10", + 0b01011 <-> "x11", + 0b01100 <-> "x12", + 0b01101 <-> "x13", + 0b01110 <-> "x14", + 0b01111 <-> "x15", + 0b10000 <-> "x16", + 0b10001 <-> "x17", + 0b10010 <-> "x18", + 0b10011 <-> "x19", + 0b10100 <-> "x20", + 0b10101 <-> "x21", + 0b10110 <-> "x22", + 0b10111 <-> "x23", + 0b11000 <-> "x24", + 0b11001 <-> "x25", + 0b11010 <-> "x26", + 0b11011 <-> "x27", + 0b11100 <-> "x28", + 0b11101 <-> "x29", + 0b11110 <-> "x30", + 0b11111 <-> "x31" } mapping creg_name : bits(3) <-> string = { - 0b000 <-> "s0", - 0b001 <-> "s1", - 0b010 <-> "a0", - 0b011 <-> "a1", - 0b100 <-> "a2", - 0b101 <-> "a3", - 0b110 <-> "a4", - 0b111 <-> "a5" + 0b000 <-> "x8", + 0b001 <-> "x9", + 0b010 <-> "x10", + 0b011 <-> "x11", + 0b100 <-> "x12", + 0b101 <-> "x13", + 0b110 <-> "x14", + 0b111 <-> "x15" } val init_base_regs : unit -> unit effect {wreg} |