Remove effects on assembly introduced in 1bb74ef9, fix effects on encdec_compressed.

4 files changed, 18 insertions, 18 deletions

diff --git a/model/riscv_insts_begin.sail b/model/riscv_insts_begin.sail
index 661a353..4ab4cfb 100644
--- a/model/riscv_insts_begin.sail
+++ b/model/riscv_insts_begin.sail
@@ -15,5 +15,5 @@ scattered mapping assembly
 val encdec : ast <-> bits(32) effect {rreg}
 scattered mapping encdec
 
-val encdec_compressed : ast <-> bits(16)
+val encdec_compressed : ast <-> bits(16) effect {rreg}
 scattered mapping encdec_compressed
diff --git a/model/riscv_insts_cdext.sail b/model/riscv_insts_cdext.sail
index 63277a8..744d199 100644
--- a/model/riscv_insts_cdext.sail
+++ b/model/riscv_insts_cdext.sail
@@ -19,9 +19,9 @@ function clause execute (C_FLDSP(uimm, rd)) = {
 }
 
 mapping clause assembly = C_FLDSP(uimm, rd)
-      if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt()
+      if (sizeof(xlen) == 32 | sizeof(xlen) == 64)
   <-> "c.fldsp" ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_6(uimm)
-      if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt()
+      if (sizeof(xlen) == 32 | sizeof(xlen) == 64)
 
 /* ****************************************************************** */
 union clause ast = C_FSDSP : (bits(6), regidx)
@@ -37,9 +37,9 @@ function clause execute (C_FSDSP(uimm, rs2)) = {
 }
 
 mapping clause assembly = C_FSDSP(uimm, rs2)
-      if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt()
+      if (sizeof(xlen) == 32 | sizeof(xlen) == 64)
   <-> "c.fsdsp" ^ spc() ^ reg_name(rs2) ^ sep() ^ hex_bits_6(uimm)
-      if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt()
+      if (sizeof(xlen) == 32 | sizeof(xlen) == 64)
 
 /* ****************************************************************** */
 union clause ast = C_FLD : (bits(5), cregidx, cregidx)
@@ -57,9 +57,9 @@ function clause execute (C_FLD(uimm, rsc, rdc)) = {
 }
 
 mapping clause assembly = C_FLD(uimm, rsc, rdc)
-      if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt()
+      if (sizeof(xlen) == 32 | sizeof(xlen) == 64)
   <-> "c.fld" ^ spc() ^ creg_name(rdc) ^ sep() ^ creg_name(rsc) ^ sep() ^ hex_bits_8(uimm @ 0b000)
-      if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt()
+      if (sizeof(xlen) == 32 | sizeof(xlen) == 64)
 
 /* ****************************************************************** */
 union clause ast = C_FSD : (bits(5), cregidx, cregidx)
@@ -77,6 +77,6 @@ function clause execute (C_FSD(uimm, rsc1, rsc2)) = {
 }
 
 mapping clause assembly = C_FSD(uimm, rsc1, rsc2)
-      if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt()
+      if (sizeof(xlen) == 32 | sizeof(xlen) == 64)
   <-> "c.fsd" ^ spc() ^ creg_name(rsc1) ^ sep() ^ creg_name(rsc2) ^ sep() ^ hex_bits_8(uimm @ 0b000)
-      if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt()
+      if (sizeof(xlen) == 32 | sizeof(xlen) == 64)
diff --git a/model/riscv_insts_cfext.sail b/model/riscv_insts_cfext.sail
index 08eeab8..d83aee1 100644
--- a/model/riscv_insts_cfext.sail
+++ b/model/riscv_insts_cfext.sail
@@ -19,9 +19,9 @@ function clause execute (C_FLWSP(imm, rd)) = {
 }
 
 mapping clause assembly = C_FLWSP(imm, rd)
-      if sizeof(xlen) == 32 & haveRVC() & haveFExt()
+      if sizeof(xlen) == 32
   <-> "c.flwsp" ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_6(imm)
-      if sizeof(xlen) == 32 & haveRVC() & haveFExt()
+      if sizeof(xlen) == 32
 
 /* ****************************************************************** */
 union clause ast = C_FSWSP : (bits(6), regidx)
@@ -37,9 +37,9 @@ function clause execute (C_FSWSP(uimm, rs2)) = {
 }
 
 mapping clause assembly = C_FSWSP(uimm, rd)
-      if sizeof(xlen) == 32 & haveRVC() & haveFExt()
+      if sizeof(xlen) == 32
   <-> "c.fswsp" ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_6(uimm)
-      if sizeof(xlen) == 32 & haveRVC() & haveFExt()
+      if sizeof(xlen) == 32
 
 /* ****************************************************************** */
 union clause ast = C_FLW : (bits(5), cregidx, cregidx)
@@ -57,9 +57,9 @@ function clause execute (C_FLW(uimm, rsc, rdc)) = {
 }
 
 mapping clause assembly = C_FLW(uimm, rsc, rdc)
-      if sizeof(xlen) == 32 & haveRVC() & haveFExt()
+      if sizeof(xlen) == 32
   <-> "c.flw" ^ spc() ^ creg_name(rdc) ^ sep() ^ creg_name(rsc) ^ sep() ^ hex_bits_7(uimm @ 0b00)
-      if sizeof(xlen) == 32 & haveRVC() & haveFExt()
+      if sizeof(xlen) == 32
 
 /* ****************************************************************** */
 union clause ast = C_FSW : (bits(5), cregidx, cregidx)
@@ -77,6 +77,6 @@ function clause execute (C_FSW(uimm, rsc1, rsc2)) = {
 }
 
 mapping clause assembly = C_FSW(uimm, rsc1, rsc2)
-      if sizeof(xlen) == 32 & haveRVC() & haveFExt()
+      if sizeof(xlen) == 32
   <-> "c.fsw" ^ spc() ^ creg_name(rsc1) ^ sep() ^ creg_name(rsc2) ^ sep() ^ hex_bits_7(uimm @ 0b00)
-      if sizeof(xlen) == 32 & haveRVC() & haveFExt()
+      if sizeof(xlen) == 32
diff --git a/model/riscv_insts_end.sail b/model/riscv_insts_end.sail
index 6c16417..fd90c4e 100644
--- a/model/riscv_insts_end.sail
+++ b/model/riscv_insts_end.sail
@@ -37,5 +37,5 @@ overload to_str = {print_insn}
 val decode : bits(32) -> ast effect {rreg}
 function decode bv = encdec(bv)
 
-val decodeCompressed : bits(16) -> ast effect pure
+val decodeCompressed : bits(16) -> ast effect {rreg}
 function decodeCompressed bv = encdec_compressed(bv)