Whitespace fixes to nuke tabs.no_casts

7 files changed, 15 insertions, 15 deletions

diff --git a/model/riscv_insts_aext.sail b/model/riscv_insts_aext.sail
index d2cbd38..de955f8 100644
--- a/model/riscv_insts_aext.sail
+++ b/model/riscv_insts_aext.sail
@@ -53,7 +53,7 @@ function clause execute(LOADRES(aq, rl, rs1, width, rd)) = {
             */
            match width {
              BYTE   => true,
-	     HALF   => vaddr[0..0] == 0b0,
+             HALF   => vaddr[0..0] == 0b0,
              WORD   => vaddr[1..0] == 0b00,
              DOUBLE => vaddr[2..0] == 0b000
            };
@@ -112,7 +112,7 @@ function clause execute (STORECON(aq, rl, rs2, rs1, width, rd)) = {
              */
             match width {
               BYTE   => true,
-	      HALF   => vaddr[0..0] == 0b0,
+              HALF   => vaddr[0..0] == 0b0,
               WORD   => vaddr[1..0] == 0b00,
               DOUBLE => vaddr[2..0] == 0b000
             };
diff --git a/model/riscv_insts_base.sail b/model/riscv_insts_base.sail
index a0858bf..e138e72 100644
--- a/model/riscv_insts_base.sail
+++ b/model/riscv_insts_base.sail
@@ -123,7 +123,7 @@ function clause execute (BTYPE(imm, rs2, rs1, op)) = {
         RETIRE_FAIL
       },
       Ext_ControlAddr_OK(target) => {
-	if bit_to_bool(target[1]) & (~ (haveRVC())) then {
+        if bit_to_bool(target[1]) & (~ (haveRVC())) then {
           handle_mem_exception(target, E_Fetch_Addr_Align);
           RETIRE_FAIL;
         } else {
@@ -309,9 +309,9 @@ function check_misaligned(vaddr : xlenbits, width : word_width) -> bool =
   if   plat_enable_misaligned_access() then false
   else match width {
          BYTE   => false,
-	 HALF   => vaddr[0] == bitone,
-	 WORD   => vaddr[0] == bitone | vaddr[1] == bitone,
-	 DOUBLE => vaddr[0] == bitone | vaddr[1] == bitone | vaddr[2] == bitone
+         HALF   => vaddr[0] == bitone,
+         WORD   => vaddr[0] == bitone | vaddr[1] == bitone,
+         DOUBLE => vaddr[0] == bitone | vaddr[1] == bitone | vaddr[2] == bitone
        }
 
 function clause execute(LOAD(imm, rs1, rd, is_unsigned, width, aq, rl)) = {
@@ -785,8 +785,8 @@ function clause execute SFENCE_VMA(rs1, rs2) = {
   match cur_privilege {
     User       => { handle_illegal(); RETIRE_FAIL },
     Supervisor => match (architecture(get_mstatus_SXL(mstatus)), mstatus.TVM()) {
-		    (Some(_), 0b1)  => { handle_illegal(); RETIRE_FAIL },
-		    (Some(_), 0b0) => { flush_TLB(asid, addr); RETIRE_SUCCESS },
+                    (Some(_), 0b1)  => { handle_illegal(); RETIRE_FAIL },
+                    (Some(_), 0b0) => { flush_TLB(asid, addr); RETIRE_SUCCESS },
                     (_, _)           => internal_error("unimplemented sfence architecture")
                   },
     Machine    => { flush_TLB(asid, addr); RETIRE_SUCCESS }
diff --git a/model/riscv_step.sail b/model/riscv_step.sail
index ed27c84..550e58e 100644
--- a/model/riscv_step.sail
+++ b/model/riscv_step.sail
@@ -10,7 +10,7 @@ function step(step_no : int) -> bool = {
     match dispatchInterrupt(cur_privilege) {
       Some(intr, priv) => {
         if   get_config_print_instr()
-	then print_bits("Handling interrupt: ", interruptType_to_bits(intr));
+        then print_bits("Handling interrupt: ", interruptType_to_bits(intr));
         handle_interrupt(intr, priv);
         (RETIRE_FAIL, false)
       },
diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail
index 14e5d99..8162cb8 100644
--- a/model/riscv_sys_control.sail
+++ b/model/riscv_sys_control.sail
@@ -147,7 +147,7 @@ function exception_delegatee(e : ExceptionType, p : Privilege) -> Privilege = {
   let super = bit_to_bool(medeleg.bits()[idx]);
   /* if S-mode is absent, medeleg delegates to U-mode if 'N' is supported. */
   let user  = if   haveSupMode()
-	      then super & haveNExt() & bit_to_bool(sedeleg.bits()[idx])
+              then super & haveNExt() & bit_to_bool(sedeleg.bits()[idx])
               else super & haveNExt();
   let deleg = if      haveUsrMode() & user  then User
               else if haveSupMode() & super then Supervisor
@@ -331,8 +331,8 @@ function trap_handler(del_priv : Privilege, intr : bool, c : exc_code, pc : xlen
        mstatus->SPIE() = mstatus.SIE();
        mstatus->SIE()  = 0b0;
        mstatus->SPP()  = match cur_privilege {
-			   User => 0b0,
-			   Supervisor => 0b1,
+                           User => 0b0,
+                           Supervisor => 0b1,
                            Machine => internal_error("invalid privilege for s-mode trap")
                          };
        stval           = tval(info);
diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail
index 25da335..71f39f7 100644
--- a/model/riscv_sys_regs.sail
+++ b/model/riscv_sys_regs.sail
@@ -81,7 +81,7 @@ function legalize_misa(m : Misa, v : xlenbits) -> Misa = {
   then { /* Allow modifications to C only for now. */
          let  v = Mk_Misa(v);
          /* Suppress changing C if nextPC would become misaligned. */
-	 if   v.C() == 0b0 & nextPC[1] == bitone
+         if   v.C() == 0b0 & nextPC[1] == bitone
          then m
          else update_C(m, v.C())
        }
diff --git a/model/riscv_vmem_rv32.sail b/model/riscv_vmem_rv32.sail
index 02f8141..b2dad82 100644
--- a/model/riscv_vmem_rv32.sail
+++ b/model/riscv_vmem_rv32.sail
@@ -17,7 +17,7 @@ function translationMode(priv) = {
     match arch {
       Some(RV32) => {
         let s = Mk_Satp32(satp[31..0]);
-	if s.Mode() == 0b0 then Sbare else Sv32
+        if s.Mode() == 0b0 then Sbare else Sv32
       },
       _    => internal_error("unsupported address translation arch")
     }
diff --git a/model/riscv_vmem_rv64.sail b/model/riscv_vmem_rv64.sail
index 3153983..c921629 100644
--- a/model/riscv_vmem_rv64.sail
+++ b/model/riscv_vmem_rv64.sail
@@ -24,7 +24,7 @@ function translationMode(priv) = {
       },
       Some(RV32) => {
         let s = Mk_Satp32(satp[31..0]);
-	if s.Mode() == 0b0 then Sbare else Sv32
+        if s.Mode() == 0b0 then Sbare else Sv32
       },
       _    => internal_error("unsupported address translation arch")
     }