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author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-03-05 07:45:38 -0800 |
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committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-03-05 07:45:38 -0800 |
commit | 05a41c1aadfd136f2e3cc1750239e681292fc72a (patch) | |
tree | f6447ed543304b96453957acc4b199ea472d98f8 | |
parent | c902b944f4340c837029d61f422199811b01cf7a (diff) | |
download | sail-riscv-05a41c1aadfd136f2e3cc1750239e681292fc72a.zip sail-riscv-05a41c1aadfd136f2e3cc1750239e681292fc72a.tar.gz sail-riscv-05a41c1aadfd136f2e3cc1750239e681292fc72a.tar.bz2 |
Fix a typo.
-rw-r--r-- | model/riscv_vmem_rv32.sail | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/model/riscv_vmem_rv32.sail b/model/riscv_vmem_rv32.sail index b59ceae..ae2b011 100644 --- a/model/riscv_vmem_rv32.sail +++ b/model/riscv_vmem_rv32.sail @@ -43,7 +43,7 @@ function translateAddr(vAddr, ac, rt) = { match mode { Sbare => TR_Address(vAddr), - Sv39 => match translate32(asid, ptb, vAddr, ac, effPriv, mxr, do_sum, SV32_LEVELS - 1) { + Sv32 => match translate32(asid, ptb, vAddr, ac, effPriv, mxr, do_sum, SV32_LEVELS - 1) { TR_Address(pa) => TR_Address(to_phys_addr(pa)), TR_Failure(f) => TR_Failure(translationException(ac, f)) }, |