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authorRobert Norton <rmn30@cam.ac.uk>2019-02-22 13:39:31 +0000
committerRobert Norton <rmn30@cam.ac.uk>2019-02-22 13:39:31 +0000
commit9b811f37d7cd8e8ce3dd645a6fab2ed3c1f37f8d (patch)
tree4f0f4391da7e17110ced82a4213736de50b93151
parent3993873fe77b5d6900892e5051403a17569c9a60 (diff)
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Fix off-by-one in PCC top check.
-rw-r--r--model/riscv_step.sail2
1 files changed, 1 insertions, 1 deletions
diff --git a/model/riscv_step.sail b/model/riscv_step.sail
index c0fc704..df07b5f 100644
--- a/model/riscv_step.sail
+++ b/model/riscv_step.sail
@@ -22,7 +22,7 @@ function fetch() -> FetchResult = {
F_CHERI_Err(CapEx_SealViolation, PC)
else if not(PCC.permit_execute) then
F_CHERI_Err(CapEx_PermitExecuteViolation, PC)
- else if abs_pc < pcc_base | abs_pc + 2 >= pcc_top then
+ else if abs_pc < pcc_base | abs_pc + 2 > pcc_top then
F_CHERI_Err(CapEx_LengthViolation, PC)
else if (abs_pc_bits[0] != 0b0 | (abs_pc_bits[1] != 0b0 & (~ (haveRVC()))))
then F_Error(E_Fetch_Addr_Align, PC)