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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-01-25 19:07:12 -0800 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-01-25 19:07:12 -0800 |
| commit | 802070807a98ee42d6d5c2933c2f0f1a13ae2509 (patch) | |
| tree | bb661b025b3314b2f7c1b9b95ab77390917f380f | |
| parent | 89cf6f8525ba5ecb67d29302b7cf3233e7553ba4 (diff) | |
| download | sail-riscv-802070807a98ee42d6d5c2933c2f0f1a13ae2509.zip sail-riscv-802070807a98ee42d6d5c2933c2f0f1a13ae2509.tar.gz sail-riscv-802070807a98ee42d6d5c2933c2f0f1a13ae2509.tar.bz2 | |
Account for U-mode availability in xRET.
| -rw-r--r-- | model/riscv_sys.sail | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/model/riscv_sys.sail b/model/riscv_sys.sail index d97f63e..591f496 100644 --- a/model/riscv_sys.sail +++ b/model/riscv_sys.sail @@ -966,7 +966,7 @@ function handle_exception(cur_priv : Privilege, ctl : ctl_result, mstatus->MIE() = mstatus.MPIE(); mstatus->MPIE() = true; cur_privilege = privLevel_of_bits(mstatus.MPP()); - mstatus->MPP() = privLevel_to_bits(User); + mstatus->MPP() = privLevel_to_bits(if haveUsrMode() then User else Machine); print_reg("CSR mstatus <- " ^ BitStr(mstatus.bits()) ^ " (input: " ^ BitStr(mstatus.bits()) ^ ")"); // Spike compatible log print_platform("ret-ing from " ^ prev_priv ^ " to " ^ cur_privilege); @@ -979,6 +979,7 @@ function handle_exception(cur_priv : Privilege, ctl : ctl_result, mstatus->SIE() = mstatus.SPIE(); mstatus->SPIE() = true; cur_privilege = if mstatus.SPP() == true then Supervisor else User; + /* S-mode implies that U-mode is supported (issue #331 on riscv-isa-manual). */ mstatus->SPP() = false; print_reg("CSR mstatus <- " ^ BitStr(mstatus.bits()) ^ " (input: " ^ BitStr(mstatus.bits()) ^ ")"); // Spike compatible log |