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| author | Robert Norton <rmn30@cam.ac.uk> | 2019-02-28 17:15:08 +0000 |
|---|---|---|
| committer | Robert Norton <rmn30@cam.ac.uk> | 2019-02-28 17:15:08 +0000 |
| commit | 53996581d849745bc3237a00298fd599359a4007 (patch) | |
| tree | 5a6a148671c7f259940095858f0f7c7a1617a156 | |
| parent | ed3f358357a16618ac14f45a6718337b824adeb3 (diff) | |
| download | sail-riscv-53996581d849745bc3237a00298fd599359a4007.zip sail-riscv-53996581d849745bc3237a00298fd599359a4007.tar.gz sail-riscv-53996581d849745bc3237a00298fd599359a4007.tar.bz2 | |
Initialise DDC.
| -rw-r--r-- | model/riscv_types.sail | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/model/riscv_types.sail b/model/riscv_types.sail index ea119f4..907b07c 100644 --- a/model/riscv_types.sail +++ b/model/riscv_types.sail @@ -169,6 +169,7 @@ function writeCapReg(n, cap) = { val init_regs : unit->unit effect{wreg} function init_regs () = { PCC = default_cap; + DDC = default_cap; nextPCC = default_cap; UTCC = default_cap; UScratchC = null_cap; |