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| author | Robert Norton <rmn30@cam.ac.uk> | 2019-02-26 16:57:25 +0000 |
|---|---|---|
| committer | Robert Norton <rmn30@cam.ac.uk> | 2019-02-26 16:57:25 +0000 |
| commit | 3117df96ceed70a5ad67b8d82df0c7218a287e9b (patch) | |
| tree | d8ee8200d1abedf0942d1f3303b0ecdd4d7cb48e | |
| parent | 7e18680c6fa098e4737e566a4f8c3ec12b49927f (diff) | |
| download | sail-riscv-3117df96ceed70a5ad67b8d82df0c7218a287e9b.zip sail-riscv-3117df96ceed70a5ad67b8d82df0c7218a287e9b.tar.gz sail-riscv-3117df96ceed70a5ad67b8d82df0c7218a287e9b.tar.bz2 | |
Use nextPCC instead of writing directly to PCC. Set TCCs to default on reset for backwards compatibility.
| -rw-r--r-- | model/riscv_step.sail | 1 | ||||
| -rw-r--r-- | model/riscv_sys_control.sail | 6 | ||||
| -rw-r--r-- | model/riscv_types.sail | 6 |
3 files changed, 7 insertions, 6 deletions
diff --git a/model/riscv_step.sail b/model/riscv_step.sail index df07b5f..962d9fd 100644 --- a/model/riscv_step.sail +++ b/model/riscv_step.sail @@ -117,6 +117,7 @@ function step(step_no) = { } }; PC = nextPC; + PCC = nextPCC; if retired then retire_instruction(); stepped } diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail index abd9687..b3b9ea9 100644 --- a/model/riscv_sys_control.sail +++ b/model/riscv_sys_control.sail @@ -303,7 +303,7 @@ function handle_trap(del_priv : Privilege, intr : bool, c : exc_code, pc : xlenb print_reg("CSR mstatus <- " ^ BitStr(mstatus.bits())); - PCC = MTCC; + nextPCC = MTCC; match tvec_addr(Mk_Mtvec(getCapOffsetBits(MTCC)), mcause) { Some(epc) => epc, None() => internal_error("Invalid mtvec mode") @@ -339,7 +339,7 @@ function handle_trap(del_priv : Privilege, intr : bool, c : exc_code, pc : xlenb print_reg("CSR mstatus <- " ^ BitStr(mstatus.bits())); - PCC = STCC; + nextPCC = STCC; match tvec_addr(Mk_Mtvec(getCapOffsetBits(STCC)), scause) { Some(epc) => epc, None() => internal_error("Invalid stvec mode") @@ -370,7 +370,7 @@ function handle_trap(del_priv : Privilege, intr : bool, c : exc_code, pc : xlenb print_reg("CSR mstatus <- " ^ BitStr(mstatus.bits())); - PCC = UTCC; + nextPCC = UTCC; match tvec_addr(Mk_Mtvec(getCapOffsetBits(UTCC)), ucause) { Some(epc) => epc, None() => internal_error("Invalid utvec mode") diff --git a/model/riscv_types.sail b/model/riscv_types.sail index 5e01770..419f9b6 100644 --- a/model/riscv_types.sail +++ b/model/riscv_types.sail @@ -157,13 +157,13 @@ val init_regs : unit->unit effect{wreg} function init_regs () = { PCC = default_cap; nextPCC = default_cap; - UTCC = null_cap; + UTCC = default_cap; UScratchC = null_cap; UEPCC = null_cap; - STCC = null_cap; + STCC = default_cap; SScratchC = null_cap; SEPCC = null_cap; - MTCC = null_cap; + MTCC = default_cap; MScratchC = null_cap; MEPCC = null_cap; foreach(i from 1 to 31) { |