Some changes for arch-specific initialization.

6 files changed, 61 insertions, 31 deletions

diff --git a/c_emulator/riscv_platform_impl.h b/c_emulator/riscv_platform_impl.h
index 85e25c9..2e59fd8 100644
--- a/c_emulator/riscv_platform_impl.h
+++ b/c_emulator/riscv_platform_impl.h
@@ -6,7 +6,6 @@
 /* Settings of the platform implementation. */
 
 #define DEFAULT_RSTVEC     0x00001000
-#define SAIL_XLEN          64
 
 extern bool rv_enable_dirty_update;
 extern bool rv_enable_misaligned;
diff --git a/c_emulator/riscv_sim.c b/c_emulator/riscv_sim.c
index ebcfdc9..f160cde 100644
--- a/c_emulator/riscv_sim.c
+++ b/c_emulator/riscv_sim.c
@@ -108,11 +108,17 @@ static void report_arch(void)
   exit(0);
 }
 
+static bool is_32bit_model(void)
+{
+  return zxlen_val == 32;
+}
+
 static void dump_dts(void)
 {
 #ifdef ENABLE_SPIKE
   size_t dts_len = 0;
-  struct tv_spike_t *s = tv_init("RV64IMAC", rv_ram_size, 0);
+  const char *isa = is_32bit_model() ? RV32ISA : RV64ISA;
+  struct tv_spike_t *s = tv_init(isa, rv_ram_size, 0);
   tv_get_dts(s, NULL, &dts_len);
   if (dts_len > 0) {
     unsigned char *dts = (unsigned char *)malloc(dts_len + 1);
@@ -263,7 +269,8 @@ void init_spike(const char *f, uint64_t entry, uint64_t ram_size)
 {
 #ifdef ENABLE_SPIKE
   bool mismatch = false;
-  s = tv_init("RV64IMAC", ram_size, 1);
+  const char *isa = is_32bit_model() ? RV32ISA : RV64ISA;
+  s = tv_init(isa, ram_size, 1);
   if (tv_is_dirty_enabled(s) != rv_enable_dirty_update) {
     mismatch = true;
     fprintf(stderr, "inconsistent enable-dirty-update setting: spike %s, sail %s\n",
@@ -326,7 +333,7 @@ void init_sail_reset_vector(uint64_t entry)
     0x297,                                      // auipc  t0,0x0
     0x28593 + (RST_VEC_SIZE * 4 << 20),         // addi   a1, t0, &dtb
     0xf1402573,                                 // csrr   a0, mhartid
-    SAIL_XLEN == 32 ?
+    is_32bit_model() ?
       0x0182a283u :                             // lw     t0,24(t0)
       0x0182b283u,                              // ld     t0,24(t0)
     0x28067,                                    // jr     t0
diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail
index 8a0e1cf..e231c44 100644
--- a/model/riscv_sys_control.sail
+++ b/model/riscv_sys_control.sail
@@ -423,7 +423,7 @@ function init_sys() -> unit = {
 
   mhartid     = EXTZ(0b0);
 
-  misa->MXL() = arch_to_bits(RV64);
+  misa->MXL() = arch_to_bits(if sizeof(xlen) == 32 then RV32 else RV64);
   misa->A()   = true; /* atomics */
   misa->C()   = true; /* RVC */
   misa->I()   = true; /* base integer ISA */
@@ -431,7 +431,6 @@ function init_sys() -> unit = {
   misa->U()   = true; /* user-mode */
   misa->S()   = true; /* supervisor-mode */
 
-  /* 64-bit only mode with no extensions */
   mstatus = set_mstatus_SXL(mstatus, misa.MXL());
   mstatus = set_mstatus_UXL(mstatus, misa.MXL());
   mstatus->SD()   = false;
diff --git a/ocaml_emulator/platform.ml b/ocaml_emulator/platform.ml
index 6ee2d2b..3bc996b 100644
--- a/ocaml_emulator/platform.ml
+++ b/ocaml_emulator/platform.ml
@@ -94,9 +94,10 @@ let bits_of_int64 i =
   get_slice_int (Big_int.of_int 64, Big_int.of_int64 i, Big_int.zero)
 
 let rom_size_ref = ref 0
-let make_rom start_pc =
-  let reset_vec = List.concat (List.map P.uint32_to_bytes (P.reset_vec_int start_pc)) in
-  let dtb = P.make_dtb (P.make_dts ()) in
+let make_rom arch start_pc =
+  let reset_vec =
+    List.concat (List.map P.uint32_to_bytes (P.reset_vec_int arch start_pc)) in
+  let dtb = P.make_dtb (P.make_dts arch) in
   let rom = reset_vec @ dtb in
   ( rom_size_ref := List.length rom;
     (*
@@ -155,14 +156,14 @@ let term_read () =
   bits_of_int (int_of_char c)
 
 (* returns starting value for PC, i.e. start of reset vector *)
-let init elf_file =
+let init arch elf_file =
   Elf.load_elf elf_file;
 
   print_platform (Printf.sprintf "\nRegistered htif_tohost at 0x%Lx.\n" (Big_int.to_int64 (Elf.elf_tohost ())));
   print_platform (Printf.sprintf "Registered clint at 0x%Lx (size 0x%Lx).\n%!" P.clint_base P.clint_size);
 
   let start_pc = Elf.Big_int.to_int64 (Elf.elf_entry ()) in
-  let rom = make_rom start_pc in
+  let rom = make_rom arch start_pc in
   let rom_base = Big_int.of_int64 P.rom_base in
   let rec write_rom ofs = function
     | [] -> ()
diff --git a/ocaml_emulator/platform_impl.ml b/ocaml_emulator/platform_impl.ml
index 3eb8217..f7fe853 100644
--- a/ocaml_emulator/platform_impl.ml
+++ b/ocaml_emulator/platform_impl.ml
@@ -1,4 +1,12 @@
-(* FIXME: copyright header *)
+(* architecture *)
+
+type arch =
+  | RV32
+  | RV64
+
+let str_of_arch = function
+  | RV32 -> "RV32"
+  | RV64 -> "RV64"
 
 (* int->byte converters in little-endian order *)
 
@@ -26,12 +34,14 @@ let uint64_to_bytes u = let open Int64 in
 
 let reset_vec_size = 8l;;
 
-let reset_vec_int start_pc = [
+let reset_vec_int arch start_pc = [
   0x297l;                                                 (* auipc  t0, 0x0      *)
   (let open Int32 in
    add 0x28593l (shift_left (mul reset_vec_size 4l) 20)); (* addi   a1, t0, ofs(dtb) *)
   0xf1402573l;                                            (* csrr   a0, mhartid  *)
-  0x0182b283l;                                            (* ld     t0, 24(t0)   *)
+  (match arch with
+     | RV32 -> 0x0182a283l                                (* lw     t0, 24(t0)   *)
+     | RV64 -> 0x0182b283l);                              (* ld     t0, 24(t0)   *)
   0x28067l;                                               (* jr     t0           *)
   0x0l;
   (let open Int64 in to_int32 (logand start_pc 0xffffffffL));
@@ -53,7 +63,7 @@ type mem_region = {
 }
 
 (* dts from spike *)
-let spike_dts isa_spec cpu_hz insns_per_rtc_tick mems =
+let spike_dts isa_spec mmu_spec cpu_hz insns_per_rtc_tick mems =
     "/dts-v1/;\n"
   ^ "\n"
   ^ "/ {\n"
@@ -71,7 +81,7 @@ let spike_dts isa_spec cpu_hz insns_per_rtc_tick mems =
   ^ "      status = \"okay\";\n"
   ^ "      compatible = \"riscv\";\n"
   ^ "      riscv,isa = \"" ^ isa_spec ^ "\";\n"
-  ^ "      mmu-type = \"riscv,sv39\";\n"
+  ^ "      mmu-type = \"riscv," ^ mmu_spec ^ "\";\n"
   ^ "      clock-frequency = <" ^ string_of_int cpu_hz ^ ">;\n"
   ^ "      CPU0_intc: interrupt-controller {\n"
   ^ "        #interrupt-cells = <1>;\n"
@@ -110,7 +120,11 @@ let insns_per_tick = 100;;
 let make_mems () = [{ addr = dram_base;
                       size = !dram_size_ref }];;
 
-let make_dts () = spike_dts "rv64imac" cpu_hz insns_per_tick (make_mems ());;
+let make_dts arch =
+  let isa, mmu = match arch with
+      | RV64 -> "rv64imac", "sv39"
+      | RV32 -> "rv32imac", "sv32" in
+  spike_dts isa mmu cpu_hz insns_per_tick (make_mems ());;
 
 let bytes_to_string bytes =
   String.init (List.length bytes) (fun i -> Char.chr (List.nth bytes i))
@@ -177,8 +191,8 @@ let rec term_read () =
 let show_bytes s =
   output_string stdout s
 
-let dump_dts () = show_bytes (make_dts ())
-let dump_dtb () = show_bytes (bytes_to_string (make_dtb (make_dts ())))
+let dump_dts arch = show_bytes (make_dts arch)
+let dump_dtb arch = show_bytes (bytes_to_string (make_dtb (make_dts arch)))
 
 (*
 let save_string_to_file s fname =
diff --git a/ocaml_emulator/riscv_ocaml_sim.ml b/ocaml_emulator/riscv_ocaml_sim.ml
index 05912f5..245a1fa 100644
--- a/ocaml_emulator/riscv_ocaml_sim.ml
+++ b/ocaml_emulator/riscv_ocaml_sim.ml
@@ -93,31 +93,41 @@ let options = Arg.align ([("-dump-dts",
 
 let usage_msg = "RISC-V platform options:"
 
+(* ELF architecture checks *)
+
+let get_arch () =
+  match Big_int.to_int Riscv.zxlen_val with
+    | 64 -> PI.RV64
+    | 32 -> PI.RV32
+    | n  -> failwith (Printf.sprintf "Unknown model architecture RV%d" n)
+
+let str_of_elf = function
+  | Elf.ELF_Class_64 -> "ELF64"
+  | Elf.ELF_Class_32 -> "ELF32"
+
 let elf_arg =
   Arg.parse options (fun s -> opt_file_arguments := !opt_file_arguments @ [s])
             usage_msg;
-  if !opt_dump_dts then (PI.dump_dts (); exit 0);
-  if !opt_dump_dtb then (PI.dump_dtb (); exit 0);
+  if !opt_dump_dts then (PI.dump_dts (get_arch ()); exit 0);
+  if !opt_dump_dtb then (PI.dump_dtb (get_arch ()); exit 0);
   ( match !opt_file_arguments with
       | f :: _ -> prerr_endline ("Sail/RISC-V: running ELF file " ^ f); f
       | _ -> (prerr_endline "Please provide an ELF file."; exit 0)
   )
 
-(* ELF architecture checks *)
-let str_of_elf = function
-  | Elf.ELF_Class_64 -> "ELF64"
-  | Elf.ELF_Class_32 -> "ELF32"
 let check_elf () =
-  match (Big_int.to_int Riscv.zxlen_val, Elf.elf_class ()) with
-    | (64, Elf.ELF_Class_64) ->
+  match (get_arch (), Elf.elf_class ()) with
+    | (PI.RV64, Elf.ELF_Class_64) ->
           P.print_platform "RV64 model loaded ELF64.\n"
-    | (32, Elf.ELF_Class_32) ->
+    | (PI.RV32, Elf.ELF_Class_32) ->
           P.print_platform "RV32 model loaded ELF32.\n"
-    | (n,  e) ->
-          (let msg = Printf.sprintf "\nRV%d model cannot execute %s.\n" n (str_of_elf e) in
+    | (a,  e) ->
+          (let msg = Printf.sprintf "\n%s model cannot execute %s.\n" (PI.str_of_arch a) (str_of_elf e) in
            Printf.eprintf "%s" msg;
            exit 1)
 
+(* model execution *)
+
 let run pc =
   sail_call
     (fun r ->
@@ -145,7 +155,7 @@ let () =
   Random.self_init ();
 
   let init_start = Unix.times () in
-  let pc = Platform.init elf_arg in
+  let pc = Platform.init (get_arch ()) elf_arg in
   let _  = check_elf () in
   let init_end = Unix.times () in
   let _ = run pc in