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authorJessica Clarke <jrtc27@jrtc27.com>2021-09-09 15:47:47 +0100
committerGitHub <noreply@github.com>2021-09-09 15:47:47 +0100
commit9ee2c9146658958fa4bf3a70e5c3b167a0293dbe (patch)
tree404acd4d71926e7bb4a8eb11bc10544b8915f59b
parent4768f62f9a779b254bc7dcd4a680ade794db92f4 (diff)
parentc97b89e4ccb2040f0d91fcc8e594fd741c5f7521 (diff)
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Merge pull request #105 from dylux/master
Fix incorrect SV48_Vaddr bitfield
-rw-r--r--model/riscv_vmem_common.sail2
1 files changed, 1 insertions, 1 deletions
diff --git a/model/riscv_vmem_common.sail b/model/riscv_vmem_common.sail
index 15ef600..c77eb38 100644
--- a/model/riscv_vmem_common.sail
+++ b/model/riscv_vmem_common.sail
@@ -191,7 +191,7 @@ type vaddr48 = bits(48)
type pte48 = bits(64)
bitfield SV48_Vaddr : vaddr48 = {
- VPNi : 38 .. 12,
+ VPNi : 47 .. 12,
PgOfs : 11 .. 0
}