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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2020-01-29 10:49:51 -0800 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2020-01-29 10:49:51 -0800 |
| commit | a8c7335a78790dba5da4ddfede7ab557deaeabbb (patch) | |
| tree | c7334e8730a6531c829b67ee408a9dac3690fd2f | |
| parent | 494a5f45d91cc0d04c89f0457bdcd0af18791c45 (diff) | |
| download | sail-riscv-a8c7335a78790dba5da4ddfede7ab557deaeabbb.zip sail-riscv-a8c7335a78790dba5da4ddfede7ab557deaeabbb.tar.gz sail-riscv-a8c7335a78790dba5da4ddfede7ab557deaeabbb.tar.bz2 | |
Fix rvfi build.
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | model/riscv_ext_regs.sail | 4 |
2 files changed, 4 insertions, 2 deletions
@@ -234,7 +234,7 @@ c_emulator/riscv_sim_$(ARCH): generated_definitions/c/riscv_model_$(ARCH).c $(C_ generated_definitions/c/riscv_rvfi_model_$(ARCH).c: $(SAIL_RVFI_SRCS) model/main.sail Makefile mkdir -p generated_definitions/c - $(SAIL) $(SAIL_FLAGS) -O -memo_z3 -c -c_include riscv_prelude.h -c_include riscv_platform.h -c_no_main $(SAIL_RVFI_SRCS) model/main.sail -o $(basename $@) + $(SAIL) $(SAIL_FLAGS) -O -Oconstant_fold -memo_z3 -c -c_include riscv_prelude.h -c_include riscv_platform.h -c_no_main $(SAIL_RVFI_SRCS) model/main.sail -o $(basename $@) sed -i -e '/^[[:space:]]*$$/d' $@ c_emulator/riscv_rvfi_$(ARCH): generated_definitions/c/riscv_rvfi_model_$(ARCH).c $(C_INCS) $(C_SRCS) $(SOFTFLOAT_LIBS) Makefile diff --git a/model/riscv_ext_regs.sail b/model/riscv_ext_regs.sail index b03ecd5..be99a8a 100644 --- a/model/riscv_ext_regs.sail +++ b/model/riscv_ext_regs.sail @@ -11,7 +11,9 @@ to be initialised differently (e.g. CHERI cap regs are initialised to omnipotent instead of null). */ val ext_rvfi_init : unit -> unit effect {wreg} -function ext_rvfi_init () = () +function ext_rvfi_init () = { + x1 = x1 // to avoid hook being optimized out +} /*! |