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authorPrashanth Mundkur <prashanth.mundkur@gmail.com>2019-06-17 19:09:27 -0700
committerPrashanth Mundkur <prashanth.mundkur@gmail.com>2019-06-17 19:09:27 -0700
commit918afe11c45fe207bd15ca0d9d79afe8a20de4c7 (patch)
treeaa649fce289cba8eb94281130ca838cab7c0bed5
parent5dc38f37b871af7d6d1af9dfbbb203fb92d99d6a (diff)
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Add basic PMP definitions.
-rw-r--r--Makefile2
-rw-r--r--model/riscv_pmp_regs.sail25
2 files changed, 26 insertions, 1 deletions
diff --git a/Makefile b/Makefile
index 50feac8..ad3d47d 100644
--- a/Makefile
+++ b/Makefile
@@ -45,7 +45,7 @@ endif
# Non-instruction sources
PRELUDE = prelude.sail prelude_mapping.sail $(SAIL_XLEN) prelude_mem_metadata.sail prelude_mem.sail
-SAIL_REGS_SRCS = riscv_reg_type.sail riscv_regs.sail riscv_pc_access.sail riscv_sys_regs.sail riscv_ext_regs.sail $(SAIL_CHECK_SRCS)
+SAIL_REGS_SRCS = riscv_reg_type.sail riscv_regs.sail riscv_pc_access.sail riscv_sys_regs.sail riscv_pmp_regs.sail riscv_ext_regs.sail $(SAIL_CHECK_SRCS)
SAIL_ARCH_SRCS = $(PRELUDE) riscv_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail
SAIL_ARCH_SRCS += riscv_mem.sail $(SAIL_VM_SRCS)
SAIL_ARCH_RVFI_SRCS = $(PRELUDE) rvfi_dii.sail riscv_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail riscv_mem.sail $(SAIL_VM_SRCS)
diff --git a/model/riscv_pmp_regs.sail b/model/riscv_pmp_regs.sail
new file mode 100644
index 0000000..2326cc7
--- /dev/null
+++ b/model/riscv_pmp_regs.sail
@@ -0,0 +1,25 @@
+enum PmpAddrmatchType = {OFF, TOR, NA4, NAPOT}
+
+bitfield Pmpcfg_ent : bits(8) = {
+ L : 7, /* locking */
+ A : 4 .. 3, /* address matching */
+ // permissions:
+ X : 2, /* execute */
+ W : 1, /* write */
+ R : 0 /* read */
+}
+
+type Pmpcfg_reg = vector(xlen_bytes, dec, Pmpcfg_ent)
+
+register Pmpcfg0 : Pmpcfg_reg
+register Pmpcfg1 : Pmpcfg_reg
+register Pmpcfg2 : Pmpcfg_reg
+register Pmpcfg3 : Pmpcfg_reg
+
+bitfield Pmp_addr_64 : bits(64) = {
+ addr : 53 .. 0
+}
+
+bitfield Pmp_addr_32 : bits(64) = {
+ addr : 31 .. 0
+}