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| author | dylux <kct30@cam.ac.uk> | 2021-08-22 01:39:42 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-08-22 01:39:42 +0800 |
| commit | c97b89e4ccb2040f0d91fcc8e594fd741c5f7521 (patch) | |
| tree | d68463a970e929ddbe518bf1c3ee449413434e94 | |
| parent | cf099be2a1aff1f326dc855875d5732607e28752 (diff) | |
| download | sail-riscv-c97b89e4ccb2040f0d91fcc8e594fd741c5f7521.zip sail-riscv-c97b89e4ccb2040f0d91fcc8e594fd741c5f7521.tar.gz sail-riscv-c97b89e4ccb2040f0d91fcc8e594fd741c5f7521.tar.bz2 | |
Fix incorrect SV48_Vaddr bitfield
| -rw-r--r-- | model/riscv_vmem_common.sail | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/model/riscv_vmem_common.sail b/model/riscv_vmem_common.sail index 15ef600..c77eb38 100644 --- a/model/riscv_vmem_common.sail +++ b/model/riscv_vmem_common.sail @@ -191,7 +191,7 @@ type vaddr48 = bits(48) type pte48 = bits(64) bitfield SV48_Vaddr : vaddr48 = { - VPNi : 38 .. 12, + VPNi : 47 .. 12, PgOfs : 11 .. 0 } |