Update the docs for the virtual memory and exception-code extensions.

3 files changed, 28 insertions, 14 deletions

diff --git a/doc/ExtendingGuide.md b/doc/ExtendingGuide.md
index a13ec94..60e45db 100644
--- a/doc/ExtendingGuide.md
+++ b/doc/ExtendingGuide.md
@@ -44,7 +44,9 @@ exception.  This is supported using the `ext` field in the
 `sync_exception` type in `riscv_sync_exception.sail`, which is where
 the extension can store this information.  The addresses involved in
 exception handling can be modified by following the interface provided
-in `riscv_sys_exceptions.sail`.
+in `riscv_sys_exceptions.sail`.  New exception codes can be introduced
+using the `E_Extension` variant of the `ExceptionType` in
+`riscv_types`.
 
 Adding low-level platform functionality
 ---------------------------------------
@@ -64,8 +66,8 @@ If this functionality requires the definition of new interrupt
 sources, their encodings would need to be added to `riscv_types.sail`,
 and their delegation and handling added to `riscv_sys_control.sail`.
 
-Modifying memory access
------------------------
+Modifying physical memory access
+--------------------------------
 
 Physical memory addressing and access is defined in `riscv_mem.sail`.
 Any new regions of memory that are accessible via physical addresses
@@ -84,12 +86,23 @@ to any newly defined architectural state.  One can examine how normal
 physical memory access is implemented in `riscv_mem.sail` with helpers
 in `prelude_mem.sail` and `prelude_mem_metadata.sail`.
 
+Extending virtual memory and address translation
+------------------------------------------------
+
 Virtual memory is implemented in `riscv_vmem.sail`, and defining new
-address translation schemes will require modifying the
-top-level `translateAddr` function.  Any access control checks on
-virtual addresses and the specifics of the new address translation can be
-specified in a separate file.  This functionality can access any newly
-defined architectural state.
+address translation schemes will require modifying the top-level
+`translateAddr` function.  New types of memory access can be defined
+using the definitions in `riscv_vmem_types`.  Any access control
+checks on virtual addresses and the specifics of the new address
+translation can be specified in a separate file.  This functionality
+can access any newly defined architectural state.
+
+The RV64 architecture has reserved bits in the PTE that can be
+utilized for research experimentation.  These bits can be accessed and
+modified using the `ext_pte` argument in functions implementing the
+page-table walk.  The information computed by and used during the
+page-table can also be varied using the `ext_ptw` argument, which can
+be defined and used by extensions as needed.
 
 Checking and transforming memory addresses
 ------------------------------------------
diff --git a/doc/ReadingGuide.md b/doc/ReadingGuide.md
index 50f865d..1e77a33 100644
--- a/doc/ReadingGuide.md
+++ b/doc/ReadingGuide.md
@@ -77,10 +77,11 @@ such as the platform memory map.
   are used in the weak memory concurrency model.
 
 - The `riscv_vmem_*.sail` files describe the S-mode address
-  translation.  `riscv_vmem_common.sail` contains the definitions and
-  processing of the page-table entries and their various permission
-  and status bits.  `riscv_vmem_sv32.sail`, `riscv_vmem_sv39.sail`,
-  and `riscv_vmem_sv48.sail` contain the specifications for the
+  translation.  `riscv_vmem_types` and `riscv_vmem_common.sail`
+  contain the definitions and processing of the page-table entries and
+  their various permission and status bits.  `riscv_types_ext`,
+  `riscv_vmem_sv32.sail`, `riscv_vmem_sv39.sail`, and
+  `riscv_vmem_sv48.sail` contain the specifications for the
   corresponding page-table walks, and `riscv_vmem_rv32.sail` and
   `riscv_vmem_rv64.sail` describe the top-level address translation
   for the corresponding architectures.
diff --git a/doc/figs/riscvspecdeps.tex b/doc/figs/riscvspecdeps.tex
index 1d937e5..212f477 100644
--- a/doc/figs/riscvspecdeps.tex
+++ b/doc/figs/riscvspecdeps.tex
@@ -34,8 +34,8 @@
   % compute location for virtmem
   \coordinate (vmloc) at ($(types)!3!(pmp)$);
   \node (virtmem) [spec] at (vmloc)              {\textbf{virtual memory}\\
-                                                     PTE formats, TLB (\texttt{riscv\_vmem\_common})\\
-                                                     page table walks (\texttt{riscv\_vmem\_svNN})\\
+                                                     PTE formats, TLB (\texttt{riscv\_vmem\_\{types,common\}})\\
+                                                     page table walks (\texttt{riscv\_types\_ext},\texttt{riscv\_vmem\_svNN})\\
                                                      address translation (\texttt{riscv\_vmem\_rvNN})};