diff options
author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2020-02-06 14:10:27 -0800 |
---|---|---|
committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2020-02-06 14:21:41 -0800 |
commit | e5b90b4843b0fec10e3594f13c6542bf5f39452b (patch) | |
tree | c852c847a1fcd32e7cbf92f6aac33e7d04ebc596 | |
parent | c8ecb8179c54a609ac7a2630aae306f6e2dcb7ac (diff) | |
download | sail-riscv-e5b90b4843b0fec10e3594f13c6542bf5f39452b.zip sail-riscv-e5b90b4843b0fec10e3594f13c6542bf5f39452b.tar.gz sail-riscv-e5b90b4843b0fec10e3594f13c6542bf5f39452b.tar.bz2 |
Handle locked TOR entries when writing PMP addresses.
Fixes #36.
-rw-r--r-- | model/riscv_insts_zicsr.sail | 32 | ||||
-rw-r--r-- | model/riscv_pmp_control.sail | 2 | ||||
-rw-r--r-- | model/riscv_pmp_regs.sail | 16 |
3 files changed, 28 insertions, 22 deletions
diff --git a/model/riscv_insts_zicsr.sail b/model/riscv_insts_zicsr.sail index 3a23d9a..3f8ccd8 100644 --- a/model/riscv_insts_zicsr.sail +++ b/model/riscv_insts_zicsr.sail @@ -122,22 +122,22 @@ function writeCSR (csr : csreg, value : xlenbits) -> unit = { (0x3A2, _) => { pmpWriteCfgReg(2, value); Some(value) }, // pmpcfg2 (0x3A3, 32) => { pmpWriteCfgReg(3, value); Some(value) }, // pmpcfg3 - (0x3B0, _) => { pmpaddr0 = pmpWriteAddr(pmp0cfg, pmpaddr0, value); Some(pmpaddr0) }, - (0x3B1, _) => { pmpaddr1 = pmpWriteAddr(pmp1cfg, pmpaddr1, value); Some(pmpaddr1) }, - (0x3B2, _) => { pmpaddr2 = pmpWriteAddr(pmp2cfg, pmpaddr2, value); Some(pmpaddr2) }, - (0x3B3, _) => { pmpaddr3 = pmpWriteAddr(pmp3cfg, pmpaddr3, value); Some(pmpaddr3) }, - (0x3B4, _) => { pmpaddr4 = pmpWriteAddr(pmp4cfg, pmpaddr4, value); Some(pmpaddr4) }, - (0x3B5, _) => { pmpaddr5 = pmpWriteAddr(pmp5cfg, pmpaddr5, value); Some(pmpaddr5) }, - (0x3B6, _) => { pmpaddr6 = pmpWriteAddr(pmp6cfg, pmpaddr6, value); Some(pmpaddr6) }, - (0x3B7, _) => { pmpaddr7 = pmpWriteAddr(pmp7cfg, pmpaddr7, value); Some(pmpaddr7) }, - (0x3B8, _) => { pmpaddr8 = pmpWriteAddr(pmp8cfg, pmpaddr8, value); Some(pmpaddr8) }, - (0x3B9, _) => { pmpaddr9 = pmpWriteAddr(pmp9cfg, pmpaddr9, value); Some(pmpaddr9) }, - (0x3BA, _) => { pmpaddr10 = pmpWriteAddr(pmp10cfg, pmpaddr10, value); Some(pmpaddr10) }, - (0x3BB, _) => { pmpaddr11 = pmpWriteAddr(pmp11cfg, pmpaddr11, value); Some(pmpaddr11) }, - (0x3BC, _) => { pmpaddr12 = pmpWriteAddr(pmp12cfg, pmpaddr12, value); Some(pmpaddr12) }, - (0x3BD, _) => { pmpaddr13 = pmpWriteAddr(pmp13cfg, pmpaddr13, value); Some(pmpaddr13) }, - (0x3BE, _) => { pmpaddr14 = pmpWriteAddr(pmp14cfg, pmpaddr14, value); Some(pmpaddr14) }, - (0x3BF, _) => { pmpaddr15 = pmpWriteAddr(pmp15cfg, pmpaddr15, value); Some(pmpaddr15) }, + (0x3B0, _) => { pmpaddr0 = pmpWriteAddr(pmpLocked(pmp0cfg), pmpTORLocked(pmp1cfg), pmpaddr0, value); Some(pmpaddr0) }, + (0x3B1, _) => { pmpaddr1 = pmpWriteAddr(pmpLocked(pmp1cfg), pmpTORLocked(pmp2cfg), pmpaddr1, value); Some(pmpaddr1) }, + (0x3B2, _) => { pmpaddr2 = pmpWriteAddr(pmpLocked(pmp2cfg), pmpTORLocked(pmp3cfg), pmpaddr2, value); Some(pmpaddr2) }, + (0x3B3, _) => { pmpaddr3 = pmpWriteAddr(pmpLocked(pmp3cfg), pmpTORLocked(pmp4cfg), pmpaddr3, value); Some(pmpaddr3) }, + (0x3B4, _) => { pmpaddr4 = pmpWriteAddr(pmpLocked(pmp4cfg), pmpTORLocked(pmp5cfg), pmpaddr4, value); Some(pmpaddr4) }, + (0x3B5, _) => { pmpaddr5 = pmpWriteAddr(pmpLocked(pmp5cfg), pmpTORLocked(pmp6cfg), pmpaddr5, value); Some(pmpaddr5) }, + (0x3B6, _) => { pmpaddr6 = pmpWriteAddr(pmpLocked(pmp6cfg), pmpTORLocked(pmp7cfg), pmpaddr6, value); Some(pmpaddr6) }, + (0x3B7, _) => { pmpaddr7 = pmpWriteAddr(pmpLocked(pmp7cfg), pmpTORLocked(pmp8cfg), pmpaddr7, value); Some(pmpaddr7) }, + (0x3B8, _) => { pmpaddr8 = pmpWriteAddr(pmpLocked(pmp8cfg), pmpTORLocked(pmp9cfg), pmpaddr8, value); Some(pmpaddr8) }, + (0x3B9, _) => { pmpaddr9 = pmpWriteAddr(pmpLocked(pmp9cfg), pmpTORLocked(pmp10cfg), pmpaddr9, value); Some(pmpaddr9) }, + (0x3BA, _) => { pmpaddr10 = pmpWriteAddr(pmpLocked(pmp10cfg), pmpTORLocked(pmp11cfg), pmpaddr10, value); Some(pmpaddr10) }, + (0x3BB, _) => { pmpaddr11 = pmpWriteAddr(pmpLocked(pmp11cfg), pmpTORLocked(pmp12cfg), pmpaddr11, value); Some(pmpaddr11) }, + (0x3BC, _) => { pmpaddr12 = pmpWriteAddr(pmpLocked(pmp12cfg), pmpTORLocked(pmp13cfg), pmpaddr12, value); Some(pmpaddr12) }, + (0x3BD, _) => { pmpaddr13 = pmpWriteAddr(pmpLocked(pmp13cfg), pmpTORLocked(pmp14cfg), pmpaddr13, value); Some(pmpaddr13) }, + (0x3BE, _) => { pmpaddr14 = pmpWriteAddr(pmpLocked(pmp14cfg), pmpTORLocked(pmp15cfg), pmpaddr14, value); Some(pmpaddr14) }, + (0x3BF, _) => { pmpaddr15 = pmpWriteAddr(pmpLocked(pmp15cfg), false, pmpaddr15, value); Some(pmpaddr15) }, /* machine mode counters */ (0xB00, _) => { mcycle[(sizeof(xlen) - 1) .. 0] = value; Some(value) }, diff --git a/model/riscv_pmp_control.sail b/model/riscv_pmp_control.sail index 4f43a6c..1970afc 100644 --- a/model/riscv_pmp_control.sail +++ b/model/riscv_pmp_control.sail @@ -40,7 +40,7 @@ function pmpCheckRWX(ent, acc) = { val pmpCheckPerms: (Pmpcfg_ent, AccessType(ext_access_type), Privilege) -> bool function pmpCheckPerms(ent, acc, priv) = { match priv { - Machine => if ent.L() == 0b1 + Machine => if pmpLocked(ent) then pmpCheckRWX(ent, acc) else true, _ => pmpCheckRWX(ent, acc) diff --git a/model/riscv_pmp_regs.sail b/model/riscv_pmp_regs.sail index 978ef18..a823a06 100644 --- a/model/riscv_pmp_regs.sail +++ b/model/riscv_pmp_regs.sail @@ -85,9 +85,15 @@ function pmpReadCfgReg(n) = { } } -/* Helper to handle locked entries */ +/* Helpers to handle locked entries */ +function pmpLocked(cfg: Pmpcfg_ent) -> bool = + cfg.L() == 0b1 + +function pmpTORLocked(cfg: Pmpcfg_ent) -> bool = + (cfg.L() == 0b1) & (pmpAddrMatchType_of_bits(cfg.A()) == TOR) + function pmpWriteCfg(cfg: Pmpcfg_ent, v: bits(8)) -> Pmpcfg_ent = - if cfg.L() == 0b1 then cfg else Mk_Pmpcfg_ent(v) + if pmpLocked(cfg) then cfg else Mk_Pmpcfg_ent(v) val pmpWriteCfgReg : forall 'n, 0 <= 'n < 4 . (atom('n), xlenbits) -> unit effect {rreg, wreg} function pmpWriteCfgReg(n, v) = { @@ -137,7 +143,7 @@ function pmpWriteCfgReg(n, v) = { } } -function pmpWriteAddr(cfg: Pmpcfg_ent, reg: xlenbits, v: xlenbits) -> xlenbits = +function pmpWriteAddr(locked: bool, tor_locked: bool, reg: xlenbits, v: xlenbits) -> xlenbits = if sizeof(xlen) == 32 - then { if cfg.L() == 0b1 then reg else v } - else { if cfg.L() == 0b1 then reg else EXTZ(v[53..0]) } + then { if (locked | tor_locked) then reg else v } + else { if (locked | tor_locked) then reg else EXTZ(v[53..0]) } |