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| author | Robert Norton <rmn30@cam.ac.uk> | 2020-08-04 19:10:39 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-08-04 19:10:39 +0100 |
| commit | 22140629433e338865f58f42423732ee108599a9 (patch) | |
| tree | 5973316ecbb12559c76137f7c5f059892f6ac71d | |
| parent | 60de68de26082dcc1a72e59a907107562d921135 (diff) | |
| download | sail-riscv-22140629433e338865f58f42423732ee108599a9.zip sail-riscv-22140629433e338865f58f42423732ee108599a9.tar.gz sail-riscv-22140629433e338865f58f42423732ee108599a9.tar.bz2 | |
Add a pointer in README to riscv-config PR
| -rw-r--r-- | README.md | 4 |
1 files changed, 4 insertions, 0 deletions
@@ -346,6 +346,10 @@ Some useful options are: configuring whether misaligned accesses trap whether page-table walks update PTE bits (`--enable-dirty-update` for C and `-enable-dirty-update` for OCaml). +### Experimental integration with riscv-config + +There is also (as yet unmerged) support for [integration with riscv-config](https://github.com/rems-project/sail-riscv/pull/43) to allow configuring the compiled model according to a riscv-config yaml specification. + ### Booting OS images For booting operating system images, see the information under the |