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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-06-25 16:10:19 -0700 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-06-25 16:10:19 -0700 |
| commit | ab8123eeb5824f23ba3d16606d85dcaad9321d93 (patch) | |
| tree | 6030e7e39767bcc49d913c48873cbfeacee85d23 | |
| parent | bbb65b3c3422d02989015a6135cf36107f10ad95 (diff) | |
| download | sail-riscv-ab8123eeb5824f23ba3d16606d85dcaad9321d93.zip sail-riscv-ab8123eeb5824f23ba3d16606d85dcaad9321d93.tar.gz sail-riscv-ab8123eeb5824f23ba3d16606d85dcaad9321d93.tar.bz2 | |
Add PMP regs to the is-defined predicate.
| -rw-r--r-- | model/riscv_sys_control.sail | 21 |
1 files changed, 20 insertions, 1 deletions
diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail index 27c2566..ed0a8de 100644 --- a/model/riscv_sys_control.sail +++ b/model/riscv_sys_control.sail @@ -28,8 +28,27 @@ function is_CSR_defined (csr : csreg, p : Privilege) -> bool = 0x343 => p == Machine, // mtval 0x344 => p == Machine, // mip - 0x3A0 => p == Machine, // pmpcfg0 + 0x3A0 => p == Machine, // pmpcfg0 + 0x3A1 => p == Machine & (sizeof(xlen) == 32), // pmpcfg1 + 0x3A2 => p == Machine, // pmpcfg2 + 0x3A3 => p == Machine & (sizeof(xlen) == 32), // pmpcfg3 + 0x3B0 => p == Machine, // pmpaddr0 + 0x3B1 => p == Machine, // pmpaddr1 + 0x3B2 => p == Machine, // pmpaddr2 + 0x3B3 => p == Machine, // pmpaddr3 + 0x3B4 => p == Machine, // pmpaddr4 + 0x3B5 => p == Machine, // pmpaddr5 + 0x3B6 => p == Machine, // pmpaddr6 + 0x3B7 => p == Machine, // pmpaddr7 + 0x3B8 => p == Machine, // pmpaddr8 + 0x3B9 => p == Machine, // pmpaddr9 + 0x3BA => p == Machine, // pmpaddrA + 0x3BB => p == Machine, // pmpaddrB + 0x3BC => p == Machine, // pmpaddrC + 0x3BD => p == Machine, // pmpaddrD + 0x3BE => p == Machine, // pmpaddrE + 0x3BF => p == Machine, // pmpaddrF /* counters */ 0xB00 => p == Machine, // mcycle |