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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-05-02 11:02:57 -0700 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-05-02 11:02:57 -0700 |
| commit | 9be6d5783ff2fa0df24691cfc3273c50528b534a (patch) | |
| tree | ca379ce217663c9b5eb888885a0831e6e7d26ce1 | |
| parent | 3c76b4a811c574452a031d95c544af40fea34d74 (diff) | |
| download | sail-riscv-9be6d5783ff2fa0df24691cfc3273c50528b534a.zip sail-riscv-9be6d5783ff2fa0df24691cfc3273c50528b534a.tar.gz sail-riscv-9be6d5783ff2fa0df24691cfc3273c50528b534a.tar.bz2 | |
rvfi: fixes for RV32
| -rw-r--r-- | model/riscv_fetch_rvfi.sail | 8 | ||||
| -rw-r--r-- | model/riscv_mem.sail | 4 | ||||
| -rw-r--r-- | model/riscv_regs.sail | 2 | ||||
| -rw-r--r-- | model/riscv_step_rvfi.sail | 2 |
4 files changed, 8 insertions, 8 deletions
diff --git a/model/riscv_fetch_rvfi.sail b/model/riscv_fetch_rvfi.sail index 1531ae1..822305a 100644 --- a/model/riscv_fetch_rvfi.sail +++ b/model/riscv_fetch_rvfi.sail @@ -5,12 +5,12 @@ function fetch() -> FetchResult = else { let i = rvfi_instruction.rvfi_insn(); rvfi_exec->rvfi_order() = minstret; - rvfi_exec->rvfi_pc_rdata() = PC; - rvfi_exec->rvfi_insn() = sail_zero_extend(i,64); + rvfi_exec->rvfi_pc_rdata() = EXTS(PC); + rvfi_exec->rvfi_insn() = EXTS(i); /* TODO: should we write these even if they're not really registers? */ - rvfi_exec->rvfi_rs1_data() = X(i[19 .. 15]); - rvfi_exec->rvfi_rs2_data() = X(i[24 .. 20]); + rvfi_exec->rvfi_rs1_data() = EXTS(X(i[19 .. 15])); + rvfi_exec->rvfi_rs2_data() = EXTS(X(i[24 .. 20])); rvfi_exec->rvfi_rs1_addr() = sail_zero_extend(i[19 .. 15],8); rvfi_exec->rvfi_rs2_addr() = sail_zero_extend(i[24 .. 20],8); diff --git a/model/riscv_mem.sail b/model/riscv_mem.sail index 85891e7..6b9d46c 100644 --- a/model/riscv_mem.sail +++ b/model/riscv_mem.sail @@ -40,7 +40,7 @@ function checked_mem_read forall 'n, 'n > 0. (t : ReadType, addr : xlenbits, wid $ifdef RVFI_DII val rvfi_read : forall 'n, 'n > 0. (xlenbits, atom('n), MemoryOpResult(bits(8 * 'n))) -> unit effect {wreg} function rvfi_read (addr, width, result) = { - rvfi_exec->rvfi_mem_addr() = addr; + rvfi_exec->rvfi_mem_addr() = EXTS(addr); match result { MemValue(v) => if width <= 8 then { rvfi_exec->rvfi_mem_rdata() = sail_zero_extend(v,64); @@ -94,7 +94,7 @@ function mem_write_ea (addr, width, aq, rl, con) = { $ifdef RVFI_DII val rvfi_write : forall 'n, 'n > 0. (xlenbits, atom('n), bits(8 * 'n)) -> unit effect {wreg} function rvfi_write (addr, width, value) = { - rvfi_exec->rvfi_mem_addr() = addr; + rvfi_exec->rvfi_mem_addr() = EXTS(addr); if width <= 8 then { rvfi_exec->rvfi_mem_wdata() = sail_zero_extend(value,64); rvfi_exec->rvfi_mem_wmask() = rvfi_encode_width_mask(width); diff --git a/model/riscv_regs.sail b/model/riscv_regs.sail index 3b656bb..cf46390 100644 --- a/model/riscv_regs.sail +++ b/model/riscv_regs.sail @@ -87,7 +87,7 @@ function rX r = { $ifdef RVFI_DII val rvfi_wX : forall 'n, 0 <= 'n < 32. (regno('n), xlenbits) -> unit effect {wreg} function rvfi_wX (r,v) = { - rvfi_exec->rvfi_rd_wdata() = v; + rvfi_exec->rvfi_rd_wdata() = EXTS(v); rvfi_exec->rvfi_rd_addr() = to_bits(8,r); } $else diff --git a/model/riscv_step_rvfi.sail b/model/riscv_step_rvfi.sail index ace7fe2..abe9394 100644 --- a/model/riscv_step_rvfi.sail +++ b/model/riscv_step_rvfi.sail @@ -6,7 +6,7 @@ function ext_pre_step_hook() -> unit = () function ext_post_step_hook() -> unit = { /* record the next pc */ - rvfi_exec->rvfi_pc_wdata() = PC + rvfi_exec->rvfi_pc_wdata() = EXTS(PC) } val ext_init : unit -> unit effect {wreg} |