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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-06-19 18:44:40 -0700 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-06-19 18:44:40 -0700 |
| commit | 42531fe799eb4025f35e57cffe0ab60c99014b63 (patch) | |
| tree | c0e4cbb4f699912abcf0c598f0cdb8d28ad21b73 | |
| parent | 67b6d4f90271f046dca0d601658f7dddf7c65dfc (diff) | |
| download | sail-riscv-42531fe799eb4025f35e57cffe0ab60c99014b63.zip sail-riscv-42531fe799eb4025f35e57cffe0ab60c99014b63.tar.gz sail-riscv-42531fe799eb4025f35e57cffe0ab60c99014b63.tar.bz2 | |
Factor out mstatus.mprv checks for effective privilege for reuse in PMP.
| -rw-r--r-- | model/riscv_sys_regs.sail | 5 | ||||
| -rw-r--r-- | model/riscv_vmem_rv32.sail | 4 | ||||
| -rw-r--r-- | model/riscv_vmem_rv64.sail | 4 |
3 files changed, 7 insertions, 6 deletions
diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail index 7b5b9e6..783785a 100644 --- a/model/riscv_sys_regs.sail +++ b/model/riscv_sys_regs.sail @@ -128,6 +128,11 @@ bitfield Mstatus : xlenbits = { } register mstatus : Mstatus +function effectivePrivilege(m : Mstatus, priv : Privilege) -> Privilege = + if m.MPRV() == true + then privLevel_of_bits(mstatus.MPP()) + else cur_privilege + function get_mstatus_SXL(m : Mstatus) -> arch_xlen = { if sizeof(xlen) == 32 then arch_to_bits(RV32) diff --git a/model/riscv_vmem_rv32.sail b/model/riscv_vmem_rv32.sail index f26e29e..d0fac76 100644 --- a/model/riscv_vmem_rv32.sail +++ b/model/riscv_vmem_rv32.sail @@ -30,9 +30,7 @@ val translateAddr : (xlenbits, AccessType, ReadType) -> TR_Result(xlenbits, Exce function translateAddr(vAddr, ac, rt) = { let effPriv : Privilege = match rt { Instruction => cur_privilege, - Data => if mstatus.MPRV() == true - then privLevel_of_bits(mstatus.MPP()) - else cur_privilege + Data => effectivePrivilege(mstatus, cur_privilege) }; let mxr : bool = mstatus.MXR() == true; let do_sum : bool = mstatus.SUM() == true; diff --git a/model/riscv_vmem_rv64.sail b/model/riscv_vmem_rv64.sail index 538dd36..cb2d1e5 100644 --- a/model/riscv_vmem_rv64.sail +++ b/model/riscv_vmem_rv64.sail @@ -37,9 +37,7 @@ val translateAddr : (xlenbits, AccessType, ReadType) -> TR_Result(xlenbits, Exce function translateAddr(vAddr, ac, rt) = { let effPriv : Privilege = match rt { Instruction => cur_privilege, - Data => if mstatus.MPRV() == true - then privLevel_of_bits(mstatus.MPP()) - else cur_privilege + Data => effectivePrivilege(mstatus, cur_privilege) }; let mxr : bool = mstatus.MXR() == true; let do_sum : bool = mstatus.SUM() == true; |