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| author | Scott Johnson <scott.johnson@arilinc.com> | 2019-05-30 10:33:29 -0700 |
|---|---|---|
| committer | Scott Johnson <scott.johnson@arilinc.com> | 2019-05-30 10:34:36 -0700 |
| commit | 3d04632291d192910d9fd7f0ff43c1680112dc3b (patch) | |
| tree | 7427486f04b222ba1134250bcc58aa3a780ca7fd | |
| parent | 65085e894d4affeb41b6758680ca1b265e92d14c (diff) | |
| download | sail-riscv-3d04632291d192910d9fd7f0ff43c1680112dc3b.zip sail-riscv-3d04632291d192910d9fd7f0ff43c1680112dc3b.tar.gz sail-riscv-3d04632291d192910d9fd7f0ff43c1680112dc3b.tar.bz2 | |
Correction to flag descriptions
| -rw-r--r-- | c_emulator/riscv_sim.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/c_emulator/riscv_sim.c b/c_emulator/riscv_sim.c index da8b73c..864e2b7 100644 --- a/c_emulator/riscv_sim.c +++ b/c_emulator/riscv_sim.c @@ -186,11 +186,11 @@ char *process_args(int argc, char **argv) rv_enable_misaligned = true; break; case 'C': - fprintf(stderr, "enabling RVC compressed instructions.\n"); + fprintf(stderr, "disabling RVC compressed instructions.\n"); rv_enable_rvc = false; break; case 'I': - fprintf(stderr, "enabling writable misa CSR.\n"); + fprintf(stderr, "disabling writable misa CSR.\n"); rv_enable_writable_misa = false; break; case 'i': |