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#
# stm32l1 devices support both JTAG and SWD transports.
#
source [find target/swj-dp.tcl]
source [find mem_helper.tcl]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME stm32l1
}
set _ENDIAN little
# Work-area is a space in RAM used for flash programming
# By default use 10kB
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
set _WORKAREASIZE 0x2800
}
# JTAG speed should be <= F_CPU/6.
# F_CPU after reset is 2MHz, so use F_JTAG max = 333kHz
adapter_khz 300
adapter_nsrst_delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
#jtag scan chain
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
if { [using_jtag] } {
# See STM Document RM0038
# Section 30.6.3 - corresponds to Cortex-M3 r2p0
set _CPUTAPID 0x4ba00477
} else {
# SWD IDCODE (single drop, arm)
set _CPUTAPID 0x2ba01477
}
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
if { [info exists BSTAPID] } {
# FIXME this never gets used to override defaults...
set _BSTAPID $BSTAPID
} else {
# See STM Document RM0038 Section 30.6.1 Rev. 12
# Low and medium density
set _BSTAPID1 0x06416041
# Cat.2 device (medium+ density)
set _BSTAPID2 0x06429041
# Cat.3 device (medium+ density)
set _BSTAPID3 0x06427041
# Cat.4 device, STM32L15/6xxD or Cat.3 device, some STM32L15/6xxC-A models
set _BSTAPID4 0x06436041
# Cat.5 device (high density), STM32L15/6xxE
set _BSTAPID5 0x06437041
}
if {[using_jtag]} {
swj_newdap $_CHIPNAME bs -irlen 5 \
-expected-id $_BSTAPID1 -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
-expected-id $_BSTAPID4 -expected-id $_BSTAPID5
}
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
# flash size will be probed
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
reset_config srst_nogate
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
}
proc stm32l_enable_HSI {} {
# Enable HSI as clock source
echo "STM32L: Enabling HSI"
# Set HSION in RCC_CR
mww 0x40023800 0x00000101
# Set HSI as SYSCLK
mww 0x40023808 0x00000001
# Increase JTAG speed
adapter_khz 2000
}
$_TARGETNAME configure -event reset-init {
stm32l_enable_HSI
}
$_TARGETNAME configure -event reset-start {
adapter_khz 300
}
$_TARGETNAME configure -event examine-end {
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
mmw 0xE0042004 0x00000007 0
# Stop watchdog counters during halt
# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
mmw 0xE0042008 0x00001800 0
}
$_TARGETNAME configure -event trace-config {
# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
# change this value accordingly to configure trace pins
# assignment
mmw 0xE0042004 0x00000020 0
}
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