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# SPDX-License-Identifier: GPL-2.0-or-later
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME pic32mx
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x30938053
}
# default working area is 16384
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
set _WORKAREASIZE 0x4000
}
adapter srst delay 100
jtag_ntrst_delay 100
#jtag scan chain
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_TARGETNAME
#
# At reset the pic32mx does not allow code execution from RAM
# we have to setup the BMX registers to allow this.
# One limitation is that we loose the first 2k of RAM.
#
global _PIC32MX_DATASIZE
global _WORKAREASIZE
set _PIC32MX_DATASIZE 0x800
set _PIC32MX_PROGSIZE [expr {$_WORKAREASIZE - $_PIC32MX_DATASIZE}]
$_TARGETNAME configure -work-area-phys 0xa0000800 -work-area-size $_PIC32MX_PROGSIZE -work-area-backup 0
$_TARGETNAME configure -event reset-init {
#
# from reset the pic32 cannot execute code in ram - enable ram execution
# minimum offset from start of ram is 2k
#
global _PIC32MX_DATASIZE
global _WORKAREASIZE
# BMXCON set 0 wait state option by clearing BMXWSDRM bit, bit 6
mww 0xbf882000 0x001f0000
# BMXDKPBA: 2k kernel data @ 0xa0000000
mww 0xbf882010 $_PIC32MX_DATASIZE
# BMXDUDBA: 14k kernel program @ 0xa0000800 - (BMXDUDBA - BMXDKPBA)
mww 0xbf882020 $_WORKAREASIZE
# BMXDUPBA: 0k user program - (BMXDUPBA - BMXDUDBA)
mww 0xbf882030 $_WORKAREASIZE
#
# Set system clock to 8Mhz if the default clock configuration is set
#
# SYSKEY register, make sure OSCCON is locked
mww 0xbf80f230 0x0
# SYSKEY register, write unlock sequence
mww 0xbf80f230 0xaa996655
mww 0xbf80f230 0x556699aa
# OSCCON register + 4, clear OSCCON FRCDIV bits: 24, 25 and 26, divided by 1
mww 0xbf80f004 0x07000000
# SYSKEY register, relock OSCCON
mww 0xbf80f230 0x0
}
set _FLASHNAME $_CHIPNAME.flash0
flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
# add virtual banks for kseg0 and kseg1
flash bank vbank0 virtual 0xbfc00000 0 0 0 $_TARGETNAME $_FLASHNAME
flash bank vbank1 virtual 0x9fc00000 0 0 0 $_TARGETNAME $_FLASHNAME
set _FLASHNAME $_CHIPNAME.flash1
flash bank $_FLASHNAME pic32mx 0x1d000000 0 0 0 $_TARGETNAME
# add virtual banks for kseg0 and kseg1
flash bank vbank2 virtual 0xbd000000 0 0 0 $_TARGETNAME $_FLASHNAME
flash bank vbank3 virtual 0x9d000000 0 0 0 $_TARGETNAME $_FLASHNAME
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