blob: c317916206003032fb7fcca7bdb59758114bb97a (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
|
source [find target/atheros_ar9344.cfg]
reset_config trst_only separate
proc ar9344_40mhz_pll_init {} {
# QCA_PLL_SRIF_CPU_DPLL2_REG
mww 0xb81161C4 0x13210f00
# QCA_PLL_SRIF_CPU_DPLL3_REG
mww 0xb81161C8 0x03000000
# QCA_PLL_SRIF_DDR_DPLL2_REG
mww 0xb8116244 0x13210f00
# QCA_PLL_SRIF_DDR_DPLL3_REG
mww 0xb8116248 0x03000000
# QCA_PLL_SRIF_BB_DPLL_BASE_REG
mww 0xb8116188 0x03000000
# QCA_PLL_CPU_DDR_CLK_CTRL_REG
mww 0xb8050008 0x0130001C
mww 0xb8050008 0x0130001C
mww 0xb8050008 0x0130001C
# QCA_PLL_CPU_PLL_CFG_REG
mww 0xb8050000 0x40021380
# QCA_PLL_DDR_PLL_CFG_REG
mww 0xb8050004 0x40815800
# QCA_PLL_CPU_DDR_CLK_CTRL_REG
mww 0xb8050008 0x0130801C
# QCA_PLL_SRIF_CPU_DPLL2_REG
mww 0xb81161C4 0x10810F00
mww 0xb81161C0 0x41C00000
# QCA_PLL_SRIF_CPU_DPLL2_REG
mww 0xb81161C4 0xD0810F00
# QCA_PLL_SRIF_CPU_DPLL3_REG
mww 0xb81161C8 0x03000000
# QCA_PLL_SRIF_CPU_DPLL2_REG
mww 0xb81161C4 0xD0800F00
# QCA_PLL_SRIF_CPU_DPLL3_REG
mww 0xb81161C8 0x03000000
# QCA_PLL_SRIF_CPU_DPLL3_REG
mww 0xb81161C8 0x43000000
# QCA_PLL_SRIF_CPU_DPLL3_REG
mww 0xb81161C8 0x030003E8
# QCA_PLL_SRIF_DDR_DPLL2_REG
mww 0xb8116244 0x10810F00
mww 0xb8116240 0x41680000
# QCA_PLL_SRIF_DDR_DPLL2_REG
mww 0xb8116244 0xD0810F00
# QCA_PLL_SRIF_DDR_DPLL3_REG
mww 0xb8116248 0x03000000
# QCA_PLL_SRIF_DDR_DPLL2_REG
mww 0xb8116244 0xD0800F00
# QCA_PLL_SRIF_DDR_DPLL3_REG
mww 0xb8116248 0x03000000
# QCA_PLL_SRIF_DDR_DPLL3_REG
mww 0xb8116248 0x43000000
# QCA_PLL_SRIF_DDR_DPLL3_REG
mww 0xb8116248 0x03000718
# QCA_PLL_CPU_DDR_CLK_CTRL_REG
mww 0xb8050008 0x01308018
mww 0xb8050008 0x01308010
mww 0xb8050008 0x01308000
# QCA_PLL_DDR_PLL_DITHER_REG
mww 0xb8050044 0x78180200
# QCA_PLL_CPU_PLL_DITHER_REG
mww 0xb8050048 0x41C00000
}
proc ar9344_ddr_init {} {
# QCA_DDR_CTRL_CFG_REG
mww 0xb8000108 0x40
# QCA_DDR_RD_DATA_THIS_CYCLE_REG
mww 0xb8000018 0xFF
# QCA_DDR_BURST_REG
mww 0xb80000C4 0x74444444
# QCA_DDR_BURST2_REG
mww 0xb80000C8 0x0222
# QCA_AHB_MASTER_TOUT_MAX_REG
mww 0xb80000CC 0xFFFFF
# QCA_DDR_CFG_REG
mww 0xb8000000 0xC7D48CD0
# QCA_DDR_CFG2_REG
mww 0xb8000004 0x9DD0E6A8
# QCA_DDR_DDR2_CFG_REG
mww 0xb80000B8 0x0E59
# QCA_DDR_CFG2_REG
mww 0xb8000004 0x9DD0E6A8
# QCA_DDR_CTRL_REG
mww 0xb8000010 0x08
mww 0xb8000010 0x08
mww 0xb8000010 0x10
mww 0xb8000010 0x20
# QCA_DDR_EMR_REG
mww 0xb800000C 0x02
# QCA_DDR_CTRL_REG
mww 0xb8000010 0x02
# QCA_DDR_MR_REG
mww 0xb8000008 0x0133
# QCA_DDR_CTRL_REG
mww 0xb8000010 0x1
mww 0xb8000010 0x8
mww 0xb8000010 0x8
mww 0xb8000010 0x4
mww 0xb8000010 0x4
# QCA_DDR_MR_REG
mww 0xb8000008 0x33
# QCA_DDR_CTRL_REG
mww 0xb8000010 0x1
# QCA_DDR_EMR_REG
mww 0xb800000C 0x0382
# QCA_DDR_CTRL_REG
mww 0xb8000010 0x2
# QCA_DDR_EMR_REG
mww 0xb800000C 0x0402
# QCA_DDR_CTRL_REG
mww 0xb8000010 0x2
# QCA_DDR_REFRESH_REG
mww 0xb8000014 0x4270
# QCA_DDR_TAP_CTRL_0_REG
mww 0xb800001C 0x0e
# QCA_DDR_TAP_CTRL_1_REG
mww 0xb8000020 0x0e
# QCA_DDR_TAP_CTRL_2_REG
mww 0xb8000024 0x0e
# QCA_DDR_TAP_CTRL_3_REG
mww 0xb8000028 0x0e
}
$_TARGETNAME configure -event reset-init {
# mww 0xb806001c 0x1000000
ar9344_40mhz_pll_init
sleep 100
# flash remap
# SPI_CONTROL_ADDR
mww 0xbF000004 0x43
ar9344_ddr_init
sleep 100
}
set ram_boot_address 0xa0000000
$_TARGETNAME configure -work-area-phys 0x1d000000 -work-area-size 0x1000
flash bank flash0 ath79 0 0 0 0 $_TARGETNAME cs0
|
