blob: 49cad5db74d281469803928175b3744f8c5ef3f4 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
|
# A PXA255 test board with SST 39LF400A flash
#
# At reset the memory map is as follows. Note that
# the memory map changes later on as the application
# starts...
#
# RAM at 0x4000000
# Flash at 0x00000000
#
source [find target/pxa255.cfg]
# Target name is set by above
$_TARGETNAME configure -work-area-phys 0x4000000 -work-area-size 0x4000 -work-area-backup 0
# flash bank <driver> <base> <size> <chip_width> <bus_width> <target> [options]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cfi 0x00000000 0x80000 2 2 $_TARGETNAME jedec_probe
proc pxa255_sst_init {} {
xscale cp15 15 0x00002001 ;#Enable CP0 and CP13 access
#
# setup GPIO
#
mww 0x40E00018 0x00008000 ;#CPSR0
sleep 20
mww 0x40E0001C 0x00000002 ;#GPSR1
sleep 20
mww 0x40E00020 0x00000008 ;#GPSR2
sleep 20
mww 0x40E0000C 0x00008000 ;#GPDR0
sleep 20
mww 0x40E00054 0x80000000 ;#GAFR0_L
sleep 20
mww 0x40E00058 0x00188010 ;#GAFR0_H
sleep 20
mww 0x40E0005C 0x60908018 ;#GAFR1_L
sleep 20
mww 0x40E0000C 0x0280E000 ;#GPDR0
sleep 20
mww 0x40E00010 0x821C88B2 ;#GPDR1
sleep 20
mww 0x40E00014 0x000F03DB ;#GPDR2
sleep 20
mww 0x40E00000 0x000F03DB ;#GPLR0
sleep 20
mww 0x40F00004 0x00000020 ;#PSSR
sleep 20
#
# setup memory controller
#
mww 0x48000008 0x01111998 ;#MSC0
sleep 20
mww 0x48000010 0x00047ff0 ;#MSC2
sleep 20
mww 0x48000014 0x00000000 ;#MECR
sleep 20
mww 0x48000028 0x00010504 ;#MCMEM0
sleep 20
mww 0x4800002C 0x00010504 ;#MCMEM1
sleep 20
mww 0x48000030 0x00010504 ;#MCATT0
sleep 20
mww 0x48000034 0x00010504 ;#MCATT1
sleep 20
mww 0x48000038 0x00004715 ;#MCIO0
sleep 20
mww 0x4800003C 0x00004715 ;#MCIO1
sleep 20
#
mww 0x48000004 0x03CA4018 ;#MDREF
sleep 20
mww 0x48000004 0x004B4018 ;#MDREF
sleep 20
mww 0x48000004 0x000B4018 ;#MDREF
sleep 20
mww 0x48000004 0x000BC018 ;#MDREF
sleep 20
mww 0x48000000 0x00001AC8 ;#MDCNFG
sleep 20
sleep 20
mww 0x48000000 0x00001AC9 ;#MDCNFG
sleep 20
mww 0x48000040 0x00000000 ;#MDMRS
sleep 20
}
$_TARGETNAME configure -event reset-init {pxa255_sst_init}
reset_config trst_and_srst
adapter_nsrst_delay 200
jtag_ntrst_delay 200
#xscale debug_handler 0 0xFFFF0800 ;# debug handler base address
|
