From 63f4e7c72a27fb828fe1be3003be6a94519e1c12 Mon Sep 17 00:00:00 2001
From: Lorenz Brun <lorenz@brun.one>
Date: Sat, 24 Dec 2022 03:56:22 +0100
Subject: target/ti-cjtag: make switching to JTAG more reliable

The current cJTAG to JTAG switching commands for TI chips are not
particularly reliable, especially on chips with accurate timing.
On a Raspberry Pi the existing sequence has (depending on cabling and
chip) a ~50% chance of working, on a much better-behaved FT2232H
it doesn't manage to enable full JTAG at all.

This change runs a bunch of test-idle cycles before actually attempting
to switch to full JTAG. This makes the switch reliable even at high
clock speeds (>100kHz) and from precise sources like the FT2232H.

Change-Id: I9293e884bf3e9606d529756ae4483b844d3c39db
Reported-by: Phil Wiggum <p1mail2015@mail.com>
Fixes: https://sourceforge.net/p/openocd/tickets/375/
Signed-off-by: Lorenz Brun <lorenz@brun.one>
Reviewed-on: https://review.openocd.org/c/openocd/+/7419
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
---
 tcl/target/ti-cjtag.cfg | 1 +
 1 file changed, 1 insertion(+)

(limited to 'tcl')

diff --git a/tcl/target/ti-cjtag.cfg b/tcl/target/ti-cjtag.cfg
index d5e13e2..97111f1 100644
--- a/tcl/target/ti-cjtag.cfg
+++ b/tcl/target/ti-cjtag.cfg
@@ -5,6 +5,7 @@
 # Read section 6.3 in http://www.ti.com/lit/pdf/swru319 for more information.
 proc ti_cjtag_to_4pin_jtag {jrc} {
 	# Bypass
+	runtest 20
 	irscan $jrc 0x3f -endstate RUN/IDLE
 	# Two zero bit scans and a one bit drshift
 	pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE
-- 
cgit v1.1


From 7335fbdbda6ff353ec878bf740721f2b13dde7ce Mon Sep 17 00:00:00 2001
From: Daniel Anselmi <danselmi@gmx.ch>
Date: Mon, 19 Jun 2023 23:37:08 +0200
Subject: tcl/board/bemicro: source cycloneiii.cfg from correct path

Change-Id: Ib1d1be1067107633949a202a05f7fd06831ba84b
Signed-off-by: Daniel Anselmi <danselmi@gmx.ch>
Reviewed-on: https://review.openocd.org/c/openocd/+/7751
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
---
 tcl/board/bemicro_cycloneiii.cfg | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tcl')

diff --git a/tcl/board/bemicro_cycloneiii.cfg b/tcl/board/bemicro_cycloneiii.cfg
index 7781bd5..95dd394 100644
--- a/tcl/board/bemicro_cycloneiii.cfg
+++ b/tcl/board/bemicro_cycloneiii.cfg
@@ -12,7 +12,7 @@ transport select jtag
 
 adapter speed 10000
 
-source [find cpld/altera-cycloneiii.cfg]
+source [find fpga/altera-cycloneiii.cfg]
 
 #quartus_cpf --option=bitstream_compression=off -c output_files\cycloneiii_blinker.sof cycloneiii_blinker.rbf
 
-- 
cgit v1.1


From 5ae0264055b2d5e5cea024aba2dd291a4d1d4ada Mon Sep 17 00:00:00 2001
From: Daniel Anselmi <danselmi@gmx.ch>
Date: Sat, 3 Jun 2023 20:16:19 +0200
Subject: pld: give devices a name for referencing in scripts

Change-Id: I05e8596ffacdb6cd8da4dd8a40bb460183f4930a
Signed-off-by: Daniel Anselmi <danselmi@gmx.ch>
Reviewed-on: https://review.openocd.org/c/openocd/+/7728
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
---
 tcl/cpld/xilinx-xc6s.cfg       | 2 +-
 tcl/cpld/xilinx-xc7.cfg        | 2 +-
 tcl/cpld/xilinx-xcu.cfg        | 2 +-
 tcl/fpga/altera-arriaii.cfg    | 2 +-
 tcl/fpga/altera-cycloneiii.cfg | 2 +-
 tcl/fpga/altera-cycloneiv.cfg  | 2 +-
 tcl/fpga/altera-cyclonev.cfg   | 2 +-
 tcl/fpga/efinix_titanium.cfg   | 2 +-
 tcl/fpga/efinix_trion.cfg      | 2 +-
 tcl/fpga/gatemate.cfg          | 2 +-
 tcl/fpga/gowin_gw1n.cfg        | 2 +-
 tcl/fpga/lattice_certus.cfg    | 2 +-
 tcl/fpga/lattice_certuspro.cfg | 2 +-
 tcl/fpga/lattice_ecp2.cfg      | 2 +-
 tcl/fpga/lattice_ecp3.cfg      | 2 +-
 tcl/fpga/lattice_ecp5.cfg      | 2 +-
 tcl/target/zynq_7000.cfg       | 2 +-
 17 files changed, 17 insertions(+), 17 deletions(-)

(limited to 'tcl')

diff --git a/tcl/cpld/xilinx-xc6s.cfg b/tcl/cpld/xilinx-xc6s.cfg
index 82b87fb..33b6d71 100644
--- a/tcl/cpld/xilinx-xc6s.cfg
+++ b/tcl/cpld/xilinx-xc6s.cfg
@@ -25,7 +25,7 @@ jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \
 	-expected-id 0x0401D093 \
 	-expected-id 0x0403D093
 
-pld device virtex2 $_CHIPNAME.tap
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap
 
 set XC6S_CFG_IN 0x05
 set XC6S_JSHUTDOWN 0x0d
diff --git a/tcl/cpld/xilinx-xc7.cfg b/tcl/cpld/xilinx-xc7.cfg
index 91a07f9..1b1cb80 100644
--- a/tcl/cpld/xilinx-xc7.cfg
+++ b/tcl/cpld/xilinx-xc7.cfg
@@ -49,7 +49,7 @@ jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \
 
 #jtag newtap $_CHIPNAME tap -irlen 38 -ignore-version -expected-id 0x036DB093
 
-pld device virtex2 $_CHIPNAME.tap 1
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap -no_jstart
 
 set XC7_JSHUTDOWN 0x0d
 set XC7_JPROGRAM 0x0b
diff --git a/tcl/cpld/xilinx-xcu.cfg b/tcl/cpld/xilinx-xcu.cfg
index 9df696d..8518e96 100644
--- a/tcl/cpld/xilinx-xcu.cfg
+++ b/tcl/cpld/xilinx-xcu.cfg
@@ -54,7 +54,7 @@ set _IRLEN [lindex $_XCU_DATA($CHIP) 1]
 # the 4 top bits (28:31) are the die stepping/revisions. ignore it.
 jtag newtap $_CHIPNAME tap -irlen $_IRLEN -ignore-version -expected-id $_EXPID
 
-pld device virtex2 $_CHIPNAME.tap 1
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap -no_jstart
 
 set XCU_JSHUTDOWN 0x0d
 set XCU_JPROGRAM 0x0b
diff --git a/tcl/fpga/altera-arriaii.cfg b/tcl/fpga/altera-arriaii.cfg
index ae752df..d59c182 100644
--- a/tcl/fpga/altera-arriaii.cfg
+++ b/tcl/fpga/altera-arriaii.cfg
@@ -28,4 +28,4 @@ jtag newtap $_CHIPNAME tap -irlen 10 \
   -expected-id 0x025030dd -expected-id 0x024820dd \
   -expected-id 0x025140dd
 
-pld device intel $_CHIPNAME.tap arriaii
+pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family arriaii
diff --git a/tcl/fpga/altera-cycloneiii.cfg b/tcl/fpga/altera-cycloneiii.cfg
index e143572..d9be645 100644
--- a/tcl/fpga/altera-cycloneiii.cfg
+++ b/tcl/fpga/altera-cycloneiii.cfg
@@ -32,4 +32,4 @@ jtag newtap $_CHIPNAME tap -irlen 10 \
   -expected-id 0x027000dd -expected-id 0x027030dd \
   -expected-id 0x027020dd
 
-pld device intel $_CHIPNAME.tap cycloneiii
+pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cycloneiii
diff --git a/tcl/fpga/altera-cycloneiv.cfg b/tcl/fpga/altera-cycloneiv.cfg
index 59243cf..6a908e8 100644
--- a/tcl/fpga/altera-cycloneiv.cfg
+++ b/tcl/fpga/altera-cycloneiv.cfg
@@ -38,4 +38,4 @@ jtag newtap $_CHIPNAME tap -irlen 10 \
   -expected-id 0x028030dd -expected-id 0x028140dd \
   -expected-id 0x028040dd
 
-pld device intel $_CHIPNAME.tap cycloneiv
+pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cycloneiv
diff --git a/tcl/fpga/altera-cyclonev.cfg b/tcl/fpga/altera-cyclonev.cfg
index 1e9c9c4..46532a5 100644
--- a/tcl/fpga/altera-cyclonev.cfg
+++ b/tcl/fpga/altera-cyclonev.cfg
@@ -44,4 +44,4 @@ jtag newtap $_CHIPNAME tap -irlen 10 \
   -expected-id 0x02d110dd -expected-id 0x02d010dd \
   -expected-id 0x02d120dd -expected-id 0x02d020dd
 
-pld device intel $_CHIPNAME.tap cyclonev
+pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cyclonev
diff --git a/tcl/fpga/efinix_titanium.cfg b/tcl/fpga/efinix_titanium.cfg
index 681b58f..8b356cb 100644
--- a/tcl/fpga/efinix_titanium.cfg
+++ b/tcl/fpga/efinix_titanium.cfg
@@ -20,4 +20,4 @@ jtag newtap $_CHIPNAME tap -irlen 5 -ignore-version \
 	-expected-id 0x00680A79 \
 	-expected-id 0x00684A79
 
-pld device efinix $_CHIPNAME.tap
+pld create $_CHIPNAME.pld efinix -chain-position $_CHIPNAME.tap
diff --git a/tcl/fpga/efinix_trion.cfg b/tcl/fpga/efinix_trion.cfg
index ecd2eda..2b50d8c 100644
--- a/tcl/fpga/efinix_trion.cfg
+++ b/tcl/fpga/efinix_trion.cfg
@@ -14,4 +14,4 @@ jtag newtap $_CHIPNAME tap -irlen 4 -ignore-version \
 	-expected-id 0x00240A79 \
 	-expected-id 0x00220A79
 
-pld device efinix $_CHIPNAME.tap
+pld create $_CHIPNAME.pld efinix -chain-position $_CHIPNAME.tap
diff --git a/tcl/fpga/gatemate.cfg b/tcl/fpga/gatemate.cfg
index cc19fd4..e8f3382 100644
--- a/tcl/fpga/gatemate.cfg
+++ b/tcl/fpga/gatemate.cfg
@@ -13,4 +13,4 @@ if { [info exists CHIPNAME] } {
 jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \
 	-expected-id 0x20000001
 
-pld device gatemate $_CHIPNAME.tap
+pld create $_CHIPNAME.pld gatemate -chain-position $_CHIPNAME.tap
diff --git a/tcl/fpga/gowin_gw1n.cfg b/tcl/fpga/gowin_gw1n.cfg
index 43d66b7..5e85066 100644
--- a/tcl/fpga/gowin_gw1n.cfg
+++ b/tcl/fpga/gowin_gw1n.cfg
@@ -26,4 +26,4 @@ jtag newtap $_CHIPNAME tap -irlen 8 -ignore-version \
 	-expected-id 0x1100181B \
 	-expected-id 0x0100481B
 
-pld device gowin $_CHIPNAME.tap
+pld create $_CHIPNAME.pld gowin -chain-position $_CHIPNAME.tap
diff --git a/tcl/fpga/lattice_certus.cfg b/tcl/fpga/lattice_certus.cfg
index 95b6e59..9ddb7d8 100644
--- a/tcl/fpga/lattice_certus.cfg
+++ b/tcl/fpga/lattice_certus.cfg
@@ -15,4 +15,4 @@ if { [info exists CHIPNAME] } {
 jtag newtap $_CHIPNAME tap -irlen 8 -irmask 0x83 -ircapture 0x1 \
 	-expected-id 0x310F1043 -expected-id 0x310F0043
 
-pld device lattice $_CHIPNAME.tap
+pld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap
diff --git a/tcl/fpga/lattice_certuspro.cfg b/tcl/fpga/lattice_certuspro.cfg
index c15a379..acaaa57 100644
--- a/tcl/fpga/lattice_certuspro.cfg
+++ b/tcl/fpga/lattice_certuspro.cfg
@@ -15,4 +15,4 @@ jtag newtap $_CHIPNAME tap -irlen 8 -irmask 0x83 -ircapture 0x1 \
 	-expected-id 0x010f4043
 #    -expected-id 0x01112043
 
-pld device lattice $_CHIPNAME.tap
+pld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap
diff --git a/tcl/fpga/lattice_ecp2.cfg b/tcl/fpga/lattice_ecp2.cfg
index a1aa2ef..5b01787 100644
--- a/tcl/fpga/lattice_ecp2.cfg
+++ b/tcl/fpga/lattice_ecp2.cfg
@@ -28,4 +28,4 @@ jtag newtap $_CHIPNAME tap -irlen 8  \
 	-expected-id 0x01271043 -expected-id 0x01272043 -expected-id 0x01274043 \
 	-expected-id 0x01273043 -expected-id 0x01275043
 
-pld device lattice $_CHIPNAME.tap
+pld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap
diff --git a/tcl/fpga/lattice_ecp3.cfg b/tcl/fpga/lattice_ecp3.cfg
index 7cd5706..21c8ffa 100644
--- a/tcl/fpga/lattice_ecp3.cfg
+++ b/tcl/fpga/lattice_ecp3.cfg
@@ -19,4 +19,4 @@ jtag newtap $_CHIPNAME tap -irlen 8  \
 	-expected-id 0x01010043 -expected-id 0x01012043 \
 	-expected-id 0x01014043 -expected-id 0x01015043
 
-pld device lattice $_CHIPNAME.tap
+pld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap
diff --git a/tcl/fpga/lattice_ecp5.cfg b/tcl/fpga/lattice_ecp5.cfg
index 4144249..cdc63f0 100644
--- a/tcl/fpga/lattice_ecp5.cfg
+++ b/tcl/fpga/lattice_ecp5.cfg
@@ -27,4 +27,4 @@ jtag newtap $_CHIPNAME tap -irlen 8 -irmask 0x83 -ircapture 0x1 \
 	-expected-id 0x41113043 -expected-id 0x81111043 -expected-id 0x81112043 \
 	-expected-id 0x81113043
 
-pld device lattice $_CHIPNAME.tap
+pld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap
diff --git a/tcl/target/zynq_7000.cfg b/tcl/target/zynq_7000.cfg
index a6f8995..014c428 100644
--- a/tcl/target/zynq_7000.cfg
+++ b/tcl/target/zynq_7000.cfg
@@ -46,7 +46,7 @@ adapter speed 1000
 ${_TARGETNAME}0 configure -event reset-assert-post "cortex_a dbginit"
 ${_TARGETNAME}1 configure -event reset-assert-post "cortex_a dbginit"
 
-pld device virtex2 zynq_pl.bs 1
+pld create zynq_pl.pld virtex2 -chain-position zynq_pl.bs -no_jstart
 
 set XC7_JSHUTDOWN 0x0d
 set XC7_JPROGRAM 0x0b
-- 
cgit v1.1


From d654e523babd26fc8d62a8fa0814c9de84826e0d Mon Sep 17 00:00:00 2001
From: Daniel Anselmi <danselmi@gmx.ch>
Date: Thu, 17 Nov 2022 02:01:04 +0100
Subject: tcl/cpld: add config files for more xilinx fpga families

Use configurable virtex pld driver to add support for more
xilinx fpga families.

Change-Id: Iff10c8c511787734fa289bdba15f03131d51e071
Signed-off-by: Daniel Anselmi <danselmi@gmx.ch>
Reviewed-on: https://review.openocd.org/c/openocd/+/7352
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
---
 tcl/cpld/xilinx-xc3s.cfg                 | 40 +++++++++++++++++++++++++++++++
 tcl/cpld/xilinx-xc4v.cfg                 | 31 ++++++++++++++++++++++++
 tcl/cpld/xilinx-xc4vfx_40_60_100_140.cfg | 22 +++++++++++++++++
 tcl/cpld/xilinx-xc5v.cfg                 | 41 ++++++++++++++++++++++++++++++++
 tcl/cpld/xilinx-xc5vfx_100_130_200.cfg   | 21 ++++++++++++++++
 tcl/cpld/xilinx-xc6s.cfg                 |  1 +
 tcl/cpld/xilinx-xc6v.cfg                 | 35 +++++++++++++++++++++++++++
 tcl/cpld/xilinx-xc7.cfg                  |  3 ++-
 tcl/target/zynq_7000.cfg                 |  1 +
 9 files changed, 194 insertions(+), 1 deletion(-)
 create mode 100644 tcl/cpld/xilinx-xc3s.cfg
 create mode 100644 tcl/cpld/xilinx-xc4v.cfg
 create mode 100644 tcl/cpld/xilinx-xc4vfx_40_60_100_140.cfg
 create mode 100644 tcl/cpld/xilinx-xc5v.cfg
 create mode 100644 tcl/cpld/xilinx-xc5vfx_100_130_200.cfg
 create mode 100644 tcl/cpld/xilinx-xc6v.cfg

(limited to 'tcl')

diff --git a/tcl/cpld/xilinx-xc3s.cfg b/tcl/cpld/xilinx-xc3s.cfg
new file mode 100644
index 0000000..a886739
--- /dev/null
+++ b/tcl/cpld/xilinx-xc3s.cfg
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx spartan3
+# https://docs.xilinx.com/v/u/en-US/ug332
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xc3s
+}
+
+# the 4 top bits (28:31) are the die stepping. ignore it.
+jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \
+	-expected-id 0x01414093 \
+	-expected-id 0x0141C093 \
+	-expected-id 0x01428093 \
+	-expected-id 0x01434093 \
+	-expected-id 0x01440093 \
+	-expected-id 0x01448093 \
+	-expected-id 0x01450093 \
+	-expected-id 0x01C10093 \
+	-expected-id 0x01C1A093 \
+	-expected-id 0x01C22093 \
+	-expected-id 0x01C2E093 \
+	-expected-id 0x01C3A093 \
+	-expected-id 0x0140C093 \
+	-expected-id 0x02210093 \
+	-expected-id 0x02218093 \
+	-expected-id 0x02220093 \
+	-expected-id 0x02228093 \
+	-expected-id 0x02230093 \
+	-expected-id 0x02610093 \
+	-expected-id 0x02618093 \
+	-expected-id 0x02620093 \
+	-expected-id 0x02628093 \
+	-expected-id 0x02630093 \
+	-expected-id 0x03840093 \
+	-expected-id 0x0384e093
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap
diff --git a/tcl/cpld/xilinx-xc4v.cfg b/tcl/cpld/xilinx-xc4v.cfg
new file mode 100644
index 0000000..3eb46eb
--- /dev/null
+++ b/tcl/cpld/xilinx-xc4v.cfg
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx virtex 4
+# https://docs.xilinx.com/v/u/en-US/ug071
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xc4v
+}
+
+# the 4 top bits (28:31) are the die stepping. ignore it.
+jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version \
+	-expected-id 0x01658093 \
+	-expected-id 0x01E58093 \
+	-expected-id 0x0167C093 \
+	-expected-id 0x02068093 \
+	-expected-id 0x01E64093 \
+	-expected-id 0x016A4093 \
+	-expected-id 0x02088093 \
+	-expected-id 0x016B4093 \
+	-expected-id 0x020B0093 \
+	-expected-id 0x016D8093 \
+	-expected-id 0x01700093 \
+	-expected-id 0x01718093 \
+	-expected-id 0x01734093
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap
+# cfg_out cfg_in jprogb jstart jshutdown user1-4
+virtex2 set_instr_codes $_CHIPNAME.pld 0x3C4 0x3C5 0x3CB 0x3CC 0x3CD
+virtex2 set_user_codes $_CHIPNAME.pld 0x3C2 0x3C3 0x3E2 0x3E3
diff --git a/tcl/cpld/xilinx-xc4vfx_40_60_100_140.cfg b/tcl/cpld/xilinx-xc4vfx_40_60_100_140.cfg
new file mode 100644
index 0000000..14dde02
--- /dev/null
+++ b/tcl/cpld/xilinx-xc4vfx_40_60_100_140.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx virtex 4
+# https://docs.xilinx.com/v/u/en-US/ug071
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xc4vfx
+}
+
+# the 4 top bits (28:31) are the die stepping. ignore it.
+jtag newtap $_CHIPNAME tap -irlen 14 -ignore-version \
+	-expected-id 0x01E8C093 \
+	-expected-id 0x01EB4093 \
+	-expected-id 0x01EE4093 \
+	-expected-id 0x01F14093 \
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap
+# cfg_out cfg_in jprogb jstart jshutdown user1-4
+virtex2 set_instr_codes $_CHIPNAME.pld 0x3FC4 0x3FC5 0x3FCB 0x3FCC 0x3FCD
+virtex2 set_user_codes $_CHIPNAME.pld 0x3FC2 0x3FC3 0x3FE2 0x3FE3
diff --git a/tcl/cpld/xilinx-xc5v.cfg b/tcl/cpld/xilinx-xc5v.cfg
new file mode 100644
index 0000000..f88bbc1
--- /dev/null
+++ b/tcl/cpld/xilinx-xc5v.cfg
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx virtex 5
+# https://docs.xilinx.com/v/u/en-US/ug191
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xc5v
+}
+
+# the 4 top bits (28:31) are the die stepping. ignore it.
+jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version \
+	-expected-id 0x0286E093 \
+	-expected-id 0x02896093 \
+	-expected-id 0x028AE093 \
+	-expected-id 0x028D6093 \
+	-expected-id 0x028EC093 \
+	-expected-id 0x0290C093 \
+	-expected-id 0x0295C093 \
+	-expected-id 0x02A56093 \
+	-expected-id 0x02A6E093 \
+	-expected-id 0x02A96093 \
+	-expected-id 0x02AAE093 \
+	-expected-id 0x02AD6093 \
+	-expected-id 0x02AEC093 \
+	-expected-id 0x02B0C093 \
+	-expected-id 0x02B5C093 \
+	-expected-id 0x02E72093 \
+	-expected-id 0x02E9A093 \
+	-expected-id 0x02ECE093 \
+	-expected-id 0x02F3E093 \
+	-expected-id 0x03276093 \
+	-expected-id 0x032C6093 \
+	-expected-id 0x04502093 \
+	-expected-id 0x0453E093
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap
+# cfg_out cfg_in jprogb jstart jshutdown user1-4
+virtex2 set_instr_codes $_CHIPNAME.pld 0x3C4 0x3C5 0x3CB 0x3CC 0x3CD
+virtex2 set_user_codes $_CHIPNAME.pld 0x3C2 0x3C3 0x3E2 0x3E3
diff --git a/tcl/cpld/xilinx-xc5vfx_100_130_200.cfg b/tcl/cpld/xilinx-xc5vfx_100_130_200.cfg
new file mode 100644
index 0000000..7420233
--- /dev/null
+++ b/tcl/cpld/xilinx-xc5vfx_100_130_200.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx virtex 5
+# https://docs.xilinx.com/v/u/en-US/ug191
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xc5vfx
+}
+
+# the 4 top bits (28:31) are the die stepping. ignore it.
+jtag newtap $_CHIPNAME tap -irlen 14 -ignore-version \
+	-expected-id 0x032D8093 \
+	-expected-id 0x03300093 \
+	-expected-id 0x03334093
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap
+# cfg_out cfg_in jprogb jstart jshutdown user1-4
+virtex2 set_instr_codes $_CHIPNAME.pld 0x3FC4 0x3FC5 0x3FCB 0x3FCC 0x3FCD
+virtex2 set_user_codes $_CHIPNAME.pld 0x3FC2 0x3FC3 0x3FE2 0x3FE3
diff --git a/tcl/cpld/xilinx-xc6s.cfg b/tcl/cpld/xilinx-xc6s.cfg
index 33b6d71..7e32094 100644
--- a/tcl/cpld/xilinx-xc6s.cfg
+++ b/tcl/cpld/xilinx-xc6s.cfg
@@ -26,6 +26,7 @@ jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \
 	-expected-id 0x0403D093
 
 pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap
+virtex2 set_user_codes $_CHIPNAME.pld 0x02 0x03 0x1A 0x1B
 
 set XC6S_CFG_IN 0x05
 set XC6S_JSHUTDOWN 0x0d
diff --git a/tcl/cpld/xilinx-xc6v.cfg b/tcl/cpld/xilinx-xc6v.cfg
new file mode 100644
index 0000000..d37439c
--- /dev/null
+++ b/tcl/cpld/xilinx-xc6v.cfg
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx virtex 6
+# https://www.xilinx.com/support/documentation/user_guides/ug360.pdf
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xc6v
+}
+
+# the 4 top bits (28:31) are the die stepping. ignore it.
+jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version \
+	-expected-id 0x042A2093 \
+	-expected-id 0x042A4093 \
+	-expected-id 0x042A8093 \
+	-expected-id 0x042AC093 \
+	-expected-id 0x04244093 \
+	-expected-id 0x0424A093 \
+	-expected-id 0x0424C093 \
+	-expected-id 0x04250093 \
+	-expected-id 0x04252093 \
+	-expected-id 0x04256093 \
+	-expected-id 0x0423A093 \
+	-expected-id 0x04286093 \
+	-expected-id 0x04288093 \
+	-expected-id 0x042C4093 \
+	-expected-id 0x042CA093 \
+	-expected-id 0x042CC093 \
+	-expected-id 0x042D0093
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap
+# cfg_out cfg_in jprogb jstart jshutdown user1-4
+virtex2 set_instr_codes $_CHIPNAME.pld 0x3C4 0x3C5 0x3CB 0x3CC 0x3CD
+virtex2 set_user_codes $_CHIPNAME.pld 0x3C2 0x3C3 0x3E2 0x3E3
diff --git a/tcl/cpld/xilinx-xc7.cfg b/tcl/cpld/xilinx-xc7.cfg
index 1b1cb80..93ec049 100644
--- a/tcl/cpld/xilinx-xc7.cfg
+++ b/tcl/cpld/xilinx-xc7.cfg
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
-# xilinx series 7 (artix, kintex, virtex)
+# xilinx series 7 (spartan, artix, kintex, virtex)
 # http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
 
 if { [info exists CHIPNAME] } {
@@ -50,6 +50,7 @@ jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \
 #jtag newtap $_CHIPNAME tap -irlen 38 -ignore-version -expected-id 0x036DB093
 
 pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap -no_jstart
+virtex2 set_user_codes $_CHIPNAME.pld 0x02 0x03 0x22 0x23
 
 set XC7_JSHUTDOWN 0x0d
 set XC7_JPROGRAM 0x0b
diff --git a/tcl/target/zynq_7000.cfg b/tcl/target/zynq_7000.cfg
index 014c428..593abd7 100644
--- a/tcl/target/zynq_7000.cfg
+++ b/tcl/target/zynq_7000.cfg
@@ -47,6 +47,7 @@ ${_TARGETNAME}0 configure -event reset-assert-post "cortex_a dbginit"
 ${_TARGETNAME}1 configure -event reset-assert-post "cortex_a dbginit"
 
 pld create zynq_pl.pld virtex2 -chain-position zynq_pl.bs -no_jstart
+virtex2 set_user_codes $zynq_pl.pld 0x02 0x03 0x22 0x23
 
 set XC7_JSHUTDOWN 0x0d
 set XC7_JPROGRAM 0x0b
-- 
cgit v1.1


From 373d7eaa706b4895cb94e5f563526aec865c8814 Mon Sep 17 00:00:00 2001
From: Daniel Anselmi <danselmi@gmx.ch>
Date: Sat, 15 Apr 2023 01:13:12 +0200
Subject: pld/virtex2: add program/refresh command

Change-Id: If6d237a6f27c4232849f73d08e7ca74276e6d464
Signed-off-by: Daniel Anselmi <danselmi@gmx.ch>
Reviewed-on: https://review.openocd.org/c/openocd/+/7714
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
---
 tcl/cpld/xilinx-xc6s.cfg | 2 ++
 tcl/cpld/xilinx-xc7.cfg  | 1 +
 tcl/cpld/xilinx-xcu.cfg  | 1 +
 tcl/target/zynq_7000.cfg | 1 +
 4 files changed, 5 insertions(+)

(limited to 'tcl')

diff --git a/tcl/cpld/xilinx-xc6s.cfg b/tcl/cpld/xilinx-xc6s.cfg
index 7e32094..92b2605 100644
--- a/tcl/cpld/xilinx-xc6s.cfg
+++ b/tcl/cpld/xilinx-xc6s.cfg
@@ -35,6 +35,7 @@ set XC6S_JSTART 0x0c
 set XC6S_BYPASS 0x3f
 
 proc xc6s_program {tap} {
+	echo "DEPRECATED! use 'virtex2 program ...' not 'xc6s_program'"
 	global XC6S_JSHUTDOWN XC6S_JPROGRAM XC6S_JSTART XC6S_BYPASS
 	irscan $tap $XC6S_JSHUTDOWN
 	irscan $tap $XC6S_JPROGRAM
@@ -44,6 +45,7 @@ proc xc6s_program {tap} {
 
 #xtp038 and xc3sprog approach
 proc xc6s_program_iprog {tap} {
+	echo "DEPRECATED! use 'virtex2 program ...' not 'xc6s_program_iprog'"
 	global XC6S_JSHUTDOWN XC6S_JSTART XC6S_BYPASS XC6S_CFG_IN
 	irscan $tap $XC6S_JSHUTDOWN
 	runtest 16
diff --git a/tcl/cpld/xilinx-xc7.cfg b/tcl/cpld/xilinx-xc7.cfg
index 93ec049..ebd76ff 100644
--- a/tcl/cpld/xilinx-xc7.cfg
+++ b/tcl/cpld/xilinx-xc7.cfg
@@ -58,6 +58,7 @@ set XC7_JSTART 0x0c
 set XC7_BYPASS 0x3f
 
 proc xc7_program {tap} {
+	echo "DEPRECATED! use 'virtex2 program ...' not 'xc7_program'"
 	global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS
 	irscan $tap $XC7_JSHUTDOWN
 	irscan $tap $XC7_JPROGRAM
diff --git a/tcl/cpld/xilinx-xcu.cfg b/tcl/cpld/xilinx-xcu.cfg
index 8518e96..2d74695 100644
--- a/tcl/cpld/xilinx-xcu.cfg
+++ b/tcl/cpld/xilinx-xcu.cfg
@@ -62,6 +62,7 @@ set XCU_JSTART 0x0c
 set XCU_BYPASS 0x3f
 
 proc xcu_program {tap} {
+	echo "DEPRECATED! use 'virtex2 program ...' not 'xcu_program'"
 	global XCU_JSHUTDOWN XCU_JPROGRAM XCU_JSTART XCU_BYPASS
 	irscan $tap $XCU_JSHUTDOWN
 	irscan $tap $XCU_JPROGRAM
diff --git a/tcl/target/zynq_7000.cfg b/tcl/target/zynq_7000.cfg
index 593abd7..f5b4478 100644
--- a/tcl/target/zynq_7000.cfg
+++ b/tcl/target/zynq_7000.cfg
@@ -55,6 +55,7 @@ set XC7_JSTART 0x0c
 set XC7_BYPASS 0x3f
 
 proc zynqpl_program {tap} {
+	echo "DEPRECATED! use 'virtex2 program ...' not 'zynqpl_program'"
 	global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS
 	irscan $tap $XC7_JSHUTDOWN
 	irscan $tap $XC7_JPROGRAM
-- 
cgit v1.1


From a27907aed1cd26bcbaac834343f08146fc8fa1fe Mon Sep 17 00:00:00 2001
From: Daniel Anselmi <danselmi@gmx.ch>
Date: Sat, 15 Apr 2023 01:13:12 +0200
Subject: ipdbg/pld: ipdbg can get tap and hub/ir from pld driver.

To start a ipdbg server one needs to know the tap and the
instruction code to reach the IPDBG-Hub. This instruction is
vendor/family specific. Knowledge which can be provided by the
pld driver.

Change-Id: I13eeb9fee895d65cd48544da4704fcc9b528b869
Signed-off-by: Daniel Anselmi <danselmi@gmx.ch>
Reviewed-on: https://review.openocd.org/c/openocd/+/7369
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
---
 tcl/fpga/efinix_titanium.cfg | 2 +-
 tcl/fpga/efinix_trion.cfg    | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'tcl')

diff --git a/tcl/fpga/efinix_titanium.cfg b/tcl/fpga/efinix_titanium.cfg
index 8b356cb..3c2cdd7 100644
--- a/tcl/fpga/efinix_titanium.cfg
+++ b/tcl/fpga/efinix_titanium.cfg
@@ -20,4 +20,4 @@ jtag newtap $_CHIPNAME tap -irlen 5 -ignore-version \
 	-expected-id 0x00680A79 \
 	-expected-id 0x00684A79
 
-pld create $_CHIPNAME.pld efinix -chain-position $_CHIPNAME.tap
+pld create $_CHIPNAME.pld efinix -chain-position $_CHIPNAME.tap -family titanium
diff --git a/tcl/fpga/efinix_trion.cfg b/tcl/fpga/efinix_trion.cfg
index 2b50d8c..1c789f5 100644
--- a/tcl/fpga/efinix_trion.cfg
+++ b/tcl/fpga/efinix_trion.cfg
@@ -14,4 +14,4 @@ jtag newtap $_CHIPNAME tap -irlen 4 -ignore-version \
 	-expected-id 0x00240A79 \
 	-expected-id 0x00220A79
 
-pld create $_CHIPNAME.pld efinix -chain-position $_CHIPNAME.tap
+pld create $_CHIPNAME.pld efinix -chain-position $_CHIPNAME.tap -family trion
-- 
cgit v1.1


From 4a96776178676963a179879624190acea1e26158 Mon Sep 17 00:00:00 2001
From: Laurent LEMELE <laurent.lemele@st.com>
Date: Tue, 13 Dec 2022 16:12:08 +0100
Subject: jtag/stlink: add STLINK-V3PWR support

STLINK-V3PWR is both a standalone debugger probe compatible with
STLINK-V3 and a source measurement unit (SMU).
Link: http://www.st.com/stlink-v3pwr

This code adds support for the debugger probe functionality.

Change-Id: Ib056e55722528f922c5574bb6fbf77e2f2b2b0c1
Signed-off-by: Laurent LEMELE <laurent.lemele@st.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7755
Tested-by: jenkins
---
 tcl/interface/stlink-dap.cfg | 2 +-
 tcl/interface/stlink.cfg     | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'tcl')

diff --git a/tcl/interface/stlink-dap.cfg b/tcl/interface/stlink-dap.cfg
index 5c24cbd..99c81c1 100644
--- a/tcl/interface/stlink-dap.cfg
+++ b/tcl/interface/stlink-dap.cfg
@@ -11,7 +11,7 @@
 #
 
 adapter driver st-link
-st-link vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753 0x0483 0x3754
+st-link vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753 0x0483 0x3754 0x0483 0x3755 0x0483 0x3757
 
 # transport select dapdirect_jtag
 # transport select dapdirect_swd
diff --git a/tcl/interface/stlink.cfg b/tcl/interface/stlink.cfg
index e4906b7..8578bf2 100644
--- a/tcl/interface/stlink.cfg
+++ b/tcl/interface/stlink.cfg
@@ -8,7 +8,7 @@
 adapter driver hla
 hla_layout stlink
 hla_device_desc "ST-LINK"
-hla_vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753 0x0483 0x3754
+hla_vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753 0x0483 0x3754 0x0483 0x3755 0x0483 0x3757
 
 # Optionally specify the serial number of ST-LINK/V2 usb device.  ST-LINK/V2
 # devices seem to have serial numbers with unreadable characters.  ST-LINK/V2
-- 
cgit v1.1


From 659f2e062d2fa2196465d2c3197da316b23285ae Mon Sep 17 00:00:00 2001
From: Daniel Anselmi <danselmi@gmx.ch>
Date: Sat, 15 Apr 2023 01:13:12 +0200
Subject: tcl/cpld: add config files for virtex-7 devices with ir-length > 6

Adding a single file for each different ir-length.

Change-Id: Iba3dd55b91c28fdb4d0cafa1ededd939fe61a267
Signed-off-by: Daniel Anselmi <danselmi@gmx.ch>
Reviewed-on: https://review.openocd.org/c/openocd/+/7715
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
---
 tcl/cpld/xilinx-xc7.cfg       |  9 ---------
 tcl/cpld/xilinx-xc7v.cfg      | 37 +++++++++++++++++++++++++++++++++++++
 tcl/cpld/xilinx-xc7vh580t.cfg | 25 +++++++++++++++++++++++++
 tcl/cpld/xilinx-xc7vh870t.cfg | 28 ++++++++++++++++++++++++++++
 4 files changed, 90 insertions(+), 9 deletions(-)
 create mode 100644 tcl/cpld/xilinx-xc7v.cfg
 create mode 100644 tcl/cpld/xilinx-xc7vh580t.cfg
 create mode 100644 tcl/cpld/xilinx-xc7vh870t.cfg

(limited to 'tcl')

diff --git a/tcl/cpld/xilinx-xc7.cfg b/tcl/cpld/xilinx-xc7.cfg
index ebd76ff..f5b0733 100644
--- a/tcl/cpld/xilinx-xc7.cfg
+++ b/tcl/cpld/xilinx-xc7.cfg
@@ -40,15 +40,6 @@ jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \
 	-expected-id 0x03691093 \
 	-expected-id 0x03696093
 
-#jtag newtap $_CHIPNAME tap -irlen 24 -ignore-version \
-#	-expected-id 0x036B3093 -expected-id 0x036B7093 \
-#	-expected-id 0x036BB093 -expected-id 0x036BF093 \
-#	-expected-id 0x036D5093
-
-#jtag newtap $_CHIPNAME tap -irlen 22 -ignore-version -expected-id 0x036D9093
-
-#jtag newtap $_CHIPNAME tap -irlen 38 -ignore-version -expected-id 0x036DB093
-
 pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap -no_jstart
 virtex2 set_user_codes $_CHIPNAME.pld 0x02 0x03 0x22 0x23
 
diff --git a/tcl/cpld/xilinx-xc7v.cfg b/tcl/cpld/xilinx-xc7v.cfg
new file mode 100644
index 0000000..8385948
--- /dev/null
+++ b/tcl/cpld/xilinx-xc7v.cfg
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx series 7 (artix, kintex, virtex)
+# http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
+# https://bsdl.info/view.htm?sid=08e275a0cd3ac38988ca59b002289d77
+# https://bsdl.info/view.htm?sid=44dae65d3cf9593188ca59b002289d77
+#
+# this config file is for XC7VX1140T and XC7V2000T only.
+# for other virtex-7 devices use xilinx-xc7vh580t.cfg or xilinx-xc7vh870t.cfg or xilinx-xc7.cfg
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xc7v
+}
+
+#0x036D5093: XC7VX1140T
+#0x036By093: XC7V2000T
+#y = xx11 = 3, 7, B or F
+
+jtag newtap $_CHIPNAME tap -irlen 24 -ignore-version \
+	-expected-id 0x036B3093 -expected-id 0x036B7093 \
+	-expected-id 0x036BB093 -expected-id 0x036BF093 \
+	-expected-id 0x036D5093
+
+#CFG_OUT_SLR0 0x124924
+#CFG_IN_SLR0  0x164924
+#CFG_OUT_SLR1 0x904924
+#CFG_IN_SLR1  0x905924
+#CFG_OUT_SLR2 0x924124
+#CFG_IN_SLR2  0x924164
+#CFG_OUT_SLR3 0x924904
+#CFG_IN_SLR3  0x924905
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap -no_jstart
+# cfg_out cfg_in jprogb jstart jshutdown
+virtex2 set_instr_codes $_CHIPNAME.pld 0x3FFFFF 0x3FFFFF 0x2CB2CB 0x30C30C 0x34D34D
diff --git a/tcl/cpld/xilinx-xc7vh580t.cfg b/tcl/cpld/xilinx-xc7vh580t.cfg
new file mode 100644
index 0000000..3748049
--- /dev/null
+++ b/tcl/cpld/xilinx-xc7vh580t.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx series 7 (artix, kintex, virtex)
+# http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
+# https://bsdl.info/view.htm?sid=65c6b2cfe1467b4988ca59b002289d77
+#
+# this config file is for xc7vh580t only.
+# for other virtex-7 devices use xilinx-xc7vh870t.cfg or xilinx-xc7v.cfg or xilinx-xc7.cfg
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xc7vh580t
+}
+
+jtag newtap $_CHIPNAME tap -irlen 22 -ignore-version -expected-id 0x036D9093
+
+#CFG_OUT_SLR0 0x0492A0
+#CFG_IN_SLR0  0x0592A0
+#CFG_OUT_SLR1 0x2412A0
+#CFG_IN_SLR1  0x2416A0
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap -no_jstart
+# cfg_out cfg_in jprogb jstart jshutdown
+virtex2 set_instr_codes $_CHIPNAME.pld 0x3FFFFF 0x3FFFFF 0x0B2EA0 0x0C32A0 0x0D36A0
diff --git a/tcl/cpld/xilinx-xc7vh870t.cfg b/tcl/cpld/xilinx-xc7vh870t.cfg
new file mode 100644
index 0000000..25e2e63
--- /dev/null
+++ b/tcl/cpld/xilinx-xc7vh870t.cfg
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx series 7 (artix, kintex, virtex)
+# http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
+# https://bsdl.info/view.htm?sid=d9ff0bb764df004588ca59b002289d77
+#
+# this config file is for xc7vh870t only.
+# for other virtex-7 devices use xilinx-xc7vh580t.cfg or xilinx-xc7v.cfg or xilinx-xc7.cfg
+#
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xc7vh870t
+}
+
+jtag newtap $_CHIPNAME tap -irlen 38 -ignore-version -expected-id 0x036DB093
+
+#CFG_OUT_SLR0 0x0492A092A0
+#CFG_IN_SLR0  0x0592A092A0
+#CFG_OUT_SLR1 0x2412A092A0
+#CFG_IN_SLR1  0x2416A092A0
+#CFG_OUT_SLR2 0x2492A012A0
+#CFG_IN_SLR2  0x2492A016A0
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap -no_jstart
+# cfg_out cfg_in jprogb jstart jshutdown
+virtex2 set_instr_codes $_CHIPNAME.pld 0x3FFFFFFFFF 0x3FFFFFFFFF 0x0B2EA02EA0 0x0C32A032A0 0x0D36A036A0
-- 
cgit v1.1


From ddf5e3f90ddf25021cebd95b908491b233c44c59 Mon Sep 17 00:00:00 2001
From: Daniel Anselmi <danselmi@gmx.ch>
Date: Sat, 15 Apr 2023 01:13:12 +0200
Subject: tcl/ultrascale: add more ultrascale devices

Add more ultrascale devices. Set instruction codes for SSI devices
such that refresh/program read_stat and user registers will work.

Change-Id: Id0a0706f4016eb8a4732725a5b72ae61efd73421
Signed-off-by: Daniel Anselmi <danselmi@gmx.ch>
Reviewed-on: https://review.openocd.org/c/openocd/+/7716
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
---
 tcl/cpld/xilinx-xcu.cfg | 99 ++++++++++++++++++++++++++++++++++++-------------
 1 file changed, 73 insertions(+), 26 deletions(-)

(limited to 'tcl')

diff --git a/tcl/cpld/xilinx-xcu.cfg b/tcl/cpld/xilinx-xcu.cfg
index 2d74695..4d7f26c 100644
--- a/tcl/cpld/xilinx-xcu.cfg
+++ b/tcl/cpld/xilinx-xcu.cfg
@@ -12,32 +12,61 @@ if { [info exists CHIPNAME] } {
 # The various chips in the Ultrascale family have different IR length.
 # Set $CHIP before including this file to determine the device.
 array set _XCU_DATA {
-	XCKU025 {0x03824093 6}
-	XCKU035 {0x03823093 6}
-	XCKU040 {0x03822093 6}
-	XCKU060 {0x03919093 6}
-	XCKU095 {0x03844093 6}
-	XCKU3P {0x04A63093 6}
-	XCKU5P {0x04A62093 6}
-	XCKU9P {0x0484A093 6}
-	XCKU11P {0x04A4E093 6}
-	XCKU13P {0x04A52093 6}
-	XCKU15P {0x04A56093 6}
-	XCVU065 {0x03939093 6}
-	XCVU080 {0x03843093 6}
-	XCVU095 {0x03842093 6}
-	XCVU3P {0x04B39093 6}
-	XCKU085 {0x0380F093 12}
-	XCKU115 {0x0390D093 12}
-	XCVU125 {0x0392D093 12}
-	XCVU5P {0x04B2B093 12}
-	XCVU7P {0x04B29093 12}
-	XCVU160 {0x03933093 18}
-	XCVU190 {0x03931093 18}
-	XCVU440 {0x0396D093 18}
-	XCVU9P {0x04B31093 18}
-	XCVU11P {0x04B49093 18}
-	XCVU13P {0x04B51093 24}
+	XCKU025         {0x03824093  6}
+	XCKU035         {0x03823093  6}
+	XCKU040         {0x03822093  6}
+	XCKU060         {0x03919093  6}
+	XCKU060_CIV     {0x0381b093  6}
+	XCKU095         {0x03844093  6}
+	XCKU095_CIV     {0x03845093  6}
+	XCKU3P          {0x04A63093  6}
+	XCKU5P          {0x04A62093  6}
+	XCKU9P          {0x0484A093  6}
+	XCKU11P         {0x04A4E093  6}
+	XCKU11P_CIV     {0x04A51093  6}
+	XCKU13P         {0x04A52093  6}
+	XCKU15P         {0x04A56093  6}
+	XCKU15P_CIV     {0x04A59093  6}
+	XCVU065         {0x03939093  6}
+	XCVU065_CIV     {0x0393b093  6}
+	XCVU080         {0x03843093  6}
+	XCVU080_CIV     {0x03845093  6}
+	XCVU095         {0x03842093  6}
+	XCVU2P          {0x04aea093  6}
+	XCVU3P          {0x04B39093  6}
+	XCVU3P_CIV      {0x04b3d093  6}
+	XCAU10P         {0x04AC4033  6}
+	XCAU10P_FFVB676 {0x04AC4093  6}
+	XCAU15P         {0x04AC2033  6}
+	XCAU15P_FFVB676 {0x04AC2093  6}
+	XCAU20P         {0x04A65093  6}
+	XCAU25P         {0x04A64093  6}
+	XCKU5P_CIV      {0x04A64093  6}
+	XCKU19P         {0x04ACF093  6}
+	XCKU19P_CIV     {0x04AD3093  6}
+	XCKU085         {0x0380F093 12}
+	XCKU115         {0x0390D093 12}
+	XCVU125         {0x0392D093 12}
+	XCVU125_CIV     {0x0392f093 12}
+	XCVU5P          {0x04B2B093 12}
+	XCVU5P_CIV      {0x04b2f093 12}
+	XCVU7P          {0x04B29093 12}
+	XCVU7P_CIV      {0x04b2d093 12}
+	XCVU160         {0x03933093 18}
+	XCVU190         {0x03931093 18}
+	XCVU440         {0x0396D093 18}
+	XCVU440_CIV     {0x0396f093 18}
+	XCVU9P          {0x04B31093 18}
+	XCVU9P_CIV      {0x04b35093 18}
+	XCVU11P         {0x04B49093 18}
+	XCVU11P_CIV     {0x04b4f093 18}
+	XCU200_FSGD2104 {0x04b37093 18}
+	XCU250          {0x04b57093 24}
+	XCVU13P         {0x04B51093 24}
+	XCVU13P_CIV     {0x04b55093 24}
+	XCVU15P         {0x04ba3093 24}
+	XCVU19P         {0x04ba1093 24}
+	XCVU19P_CIV     {0x04ba5093 24}
 }
 
 if { ![info exists CHIP] } {
@@ -56,6 +85,24 @@ jtag newtap $_CHIPNAME tap -irlen $_IRLEN -ignore-version -expected-id $_EXPID
 
 pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap -no_jstart
 
+# set the correct instruction codes for jtag hub and
+# at least the right code for jprogb, jstart and jshutdown for SSI devices
+if { $_IRLEN == 6 } {
+	virtex2 set_user_codes $_CHIPNAME.pld 0x2 0x3 0x22 0x23
+} elseif {$_IRLEN == 12 } {
+	puts "loading bitstream through jtag will not work, but reprogram (refresh)"
+	virtex2 set_instr_codes $_CHIPNAME.pld 0x905 0x904 0x2cb 0x30c 0x34d
+	virtex2 set_user_codes $_CHIPNAME.pld 0x0a4 0x0e4 0x8a4 0x8e4
+} elseif {$_IRLEN == 18 } {
+	puts "loading bitstream through jtag will not work, but reprogram (refresh)"
+	virtex2 set_instr_codes $_CHIPNAME.pld 0x24905 0x24904 0x0b2cb 0x0c30c 0x0d34d
+	virtex2 set_user_codes $_CHIPNAME.pld 0x000a4 0x000e4 0x008a4 0x008e4
+} else {
+	puts "loading bitstream through jtag will not work, but reprogram (refresh)"
+	virtex2 set_instr_codes $_CHIPNAME.pld 0x924905 0x924904 0x2cb2cb 0x30c30c 0x34d34d
+	virtex2 set_user_codes $_CHIPNAME.pld 0x0a4924 0x0e4924 0x8a4924 0x8e4924
+}
+
 set XCU_JSHUTDOWN 0x0d
 set XCU_JPROGRAM 0x0b
 set XCU_JSTART 0x0c
-- 
cgit v1.1


From c97b9054d9f52516b529bea58f09e14a4e0d82fd Mon Sep 17 00:00:00 2001
From: Erhan Kurubas <erhan.kurubas@espressif.com>
Date: Sun, 18 Jun 2023 10:17:33 +0200
Subject: tcl/target: move Espressif shared functions to esp_common.cfg

Consolidate commonly used commands and variables from
chip config files into functions in esp_common.cfg.
This includes "jtag newtap," "target create,"and "configure -event."
Enhances code reusability and simplifies maintenance.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I9e8bf07a4a15d4544ceb564607dea66837381d70
Reviewed-on: https://review.openocd.org/c/openocd/+/7744
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
---
 tcl/target/esp_common.cfg | 185 +++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 182 insertions(+), 3 deletions(-)

(limited to 'tcl')

diff --git a/tcl/target/esp_common.cfg b/tcl/target/esp_common.cfg
index 424c0cd..ac8cd6a 100644
--- a/tcl/target/esp_common.cfg
+++ b/tcl/target/esp_common.cfg
@@ -1,10 +1,189 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 #
+
+set CPU_MAX_ADDRESS 0xFFFFFFFF
+source [find bitsbytes.tcl]
+source [find memory.tcl]
+source [find mmr_helpers.tcl]
+
 # Common ESP chips definitions
 
+# Espressif supports only NuttX in the upstream.
+# FreeRTOS support is not upstreamed yet.
+set _RTOS "hwthread"
+if { [info exists ESP_RTOS] } {
+	set _RTOS "$ESP_RTOS"
+}
+
+# by default current dir (when OOCD has been started)
+set _SEMIHOST_BASEDIR "."
 if { [info exists ESP_SEMIHOST_BASEDIR] } {
 	set _SEMIHOST_BASEDIR $ESP_SEMIHOST_BASEDIR
-} else {
-	# by default current dir (when OOCD has been started)
-	set _SEMIHOST_BASEDIR "."
+}
+
+proc set_esp_common_variables { } {
+	global _CHIPNAME _ONLYCPU _ESP_SMP_TARGET
+	global _CPUNAME_0 _CPUNAME_1 _TARGETNAME_0 _TARGETNAME_1 _TAPNAME_0 _TAPNAME_1
+	global _ESP_WDT_DISABLE _ESP_SOC_RESET _ESP_MEMPROT_IS_ENABLED
+
+	# For now we support dual core at most.
+	if { $_ONLYCPU == 1 && $_ESP_SMP_TARGET == 0} {
+		set _TARGETNAME_0 				$_CHIPNAME
+		set _CPUNAME_0					cpu
+		set _TAPNAME_0 					$_CHIPNAME.$_CPUNAME_0
+	} else {
+		set _CPUNAME_0 					cpu0
+		set _CPUNAME_1 					cpu1
+		set _TARGETNAME_0 				$_CHIPNAME.$_CPUNAME_0
+		set _TARGETNAME_1 				$_CHIPNAME.$_CPUNAME_1
+		set _TAPNAME_0 					$_TARGETNAME_0
+		set _TAPNAME_1 					$_TARGETNAME_1
+	}
+
+	set _ESP_WDT_DISABLE 			"${_CHIPNAME}_wdt_disable"
+	set _ESP_SOC_RESET 				"${_CHIPNAME}_soc_reset"
+	set _ESP_MEMPROT_IS_ENABLED 	"${_CHIPNAME}_memprot_is_enabled"
+}
+
+proc create_esp_jtag { } {
+	global _CHIPNAME _CPUNAME_0 _CPUNAME_1 _CPUTAPID _ONLYCPU
+	jtag newtap $_CHIPNAME $_CPUNAME_0 -irlen 5 -expected-id $_CPUTAPID
+	if { $_ONLYCPU != 1 } {
+		jtag newtap $_CHIPNAME $_CPUNAME_1 -irlen 5 -expected-id $_CPUTAPID
+	} elseif [info exists _CPUNAME_1] {
+		jtag newtap $_CHIPNAME $_CPUNAME_1 -irlen 5 -disable -expected-id $_CPUTAPID
+	}
+}
+
+proc create_openocd_targets  { } {
+	global _TARGETNAME_0 _TARGETNAME_1 _TAPNAME_0 _TAPNAME_1 _RTOS _CHIPNAME _ONLYCPU
+
+	target create $_TARGETNAME_0 $_CHIPNAME -chain-position $_TAPNAME_0 -coreid 0 -rtos $_RTOS
+	if { $_ONLYCPU != 1 } {
+		target create $_TARGETNAME_1 $_CHIPNAME -chain-position $_TAPNAME_1 -coreid 1 -rtos $_RTOS
+		target smp $_TARGETNAME_0 $_TARGETNAME_1
+	}
+}
+
+proc create_esp_target { ARCH } {
+	set_esp_common_variables
+	create_esp_jtag
+	create_openocd_targets
+	configure_openocd_events
+
+	if { $ARCH == "xtensa"} {
+		configure_esp_xtensa_default_settings
+	} else {
+		# riscv targets are not upstreamed yet.
+		# they can be found at the official Espressif fork.
+	}
+}
+
+#################### Set event handlers and default settings  ####################
+
+proc configure_event_examine_end { } {
+	global _TARGETNAME_0 _TARGETNAME_1 _ONLYCPU
+
+	$_TARGETNAME_0 configure -event examine-end {
+		# Need to enable to set 'semihosting_basedir'
+		arm semihosting enable
+		arm semihosting_resexit enable
+		if { [info exists _SEMIHOST_BASEDIR] } {
+			if { $_SEMIHOST_BASEDIR != "" } {
+				arm semihosting_basedir $_SEMIHOST_BASEDIR
+			}
+		}
+	}
+
+	if { $_ONLYCPU != 1 } {
+		$_TARGETNAME_1 configure -event examine-end {
+			# Need to enable to set 'semihosting_basedir'
+			arm semihosting enable
+			arm semihosting_resexit enable
+			if { [info exists _SEMIHOST_BASEDIR] } {
+				if { $_SEMIHOST_BASEDIR != "" } {
+					arm semihosting_basedir $_SEMIHOST_BASEDIR
+				}
+			}
+		}
+	}
+}
+
+proc configure_event_reset_assert_post { } {
+	global _TARGETNAME_0 _TARGETNAME_1 _ONLYCPU
+
+	$_TARGETNAME_0 configure -event reset-assert-post {
+		global _ESP_SOC_RESET
+		$_ESP_SOC_RESET
+	}
+
+	if { $_ONLYCPU != 1 } {
+		$_TARGETNAME_1 configure -event reset-assert-post {
+			global _ESP_SOC_RESET
+			$_ESP_SOC_RESET
+		}
+	}
+}
+
+proc configure_event_halted { } {
+	global _TARGETNAME_0
+
+	$_TARGETNAME_0 configure -event halted {
+		global _ESP_WDT_DISABLE
+	    $_ESP_WDT_DISABLE
+	    esp halted_event_handler
+	}
+}
+
+proc configure_event_gdb_attach { } {
+	global _TARGETNAME_0 _TARGETNAME_1 _ONLYCPU
+
+	$_TARGETNAME_0 configure -event gdb-attach {
+		if { $_ESP_SMP_BREAK != 0 } {
+			$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
+		}
+		# necessary to auto-probe flash bank when GDB is connected and generate proper memory map
+		halt 1000
+		if { [$_ESP_MEMPROT_IS_ENABLED] } {
+			# 'reset halt' to disable memory protection and allow flasher to work correctly
+			echo "Memory protection is enabled. Reset target to disable it..."
+			reset halt
+		}
+	}
+
+	if { $_ONLYCPU != 1 } {
+		$_TARGETNAME_1 configure -event gdb-attach {
+			if { $_ESP_SMP_BREAK != 0 } {
+				$_TARGETNAME_1 xtensa smpbreak BreakIn BreakOut
+			}
+			# necessary to auto-probe flash bank when GDB is connected
+			halt 1000
+			if { [$_ESP_MEMPROT_IS_ENABLED] } {
+				# 'reset halt' to disable memory protection and allow flasher to work correctly
+				echo "Memory protection is enabled. Reset target to disable it..."
+				reset halt
+			}
+		}
+	}
+}
+
+proc configure_openocd_events { } {
+	configure_event_examine_end
+	configure_event_reset_assert_post
+	configure_event_gdb_attach
+}
+
+proc configure_esp_xtensa_default_settings { } {
+	global _TARGETNAME_0 _ESP_SMP_BREAK _FLASH_VOLTAGE _CHIPNAME
+
+	$_TARGETNAME_0 xtensa maskisr on
+	if { $_ESP_SMP_BREAK != 0 } {
+		$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
+	}
+
+	gdb_breakpoint_override hard
+
+	if { [info exists _FLASH_VOLTAGE] } {
+		$_TARGETNAME_0 $_CHIPNAME flashbootstrap $_FLASH_VOLTAGE
+	}
 }
-- 
cgit v1.1


From d70fd7c5be74f5f524130c95985670eb57f5d5fa Mon Sep 17 00:00:00 2001
From: Erhan Kurubas <erhan.kurubas@espressif.com>
Date: Sun, 18 Jun 2023 10:25:07 +0200
Subject: tcl/target: update esp32.cfg to reference shared functions in the
 esp_common.cfg

This commit enhances code reusability, simplifies maintenance, and ensures
consistency across all chip configurations by consolidating commonly used
commands and variables into the common config file.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I9181737d83eeba4e983b6a455b8a1523f2576dd2
Reviewed-on: https://review.openocd.org/c/openocd/+/7745
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
---
 tcl/target/esp32.cfg | 94 +++++++++-------------------------------------------
 1 file changed, 15 insertions(+), 79 deletions(-)

(limited to 'tcl')

diff --git a/tcl/target/esp32.cfg b/tcl/target/esp32.cfg
index f4c13aa..b30a170 100644
--- a/tcl/target/esp32.cfg
+++ b/tcl/target/esp32.cfg
@@ -1,99 +1,35 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 #
-# The ESP32 only supports JTAG.
-transport select jtag
 
-# Source the ESP common configuration file
+# Source the ESP common configuration file.
 source [find target/esp_common.cfg]
 
-if { [info exists CHIPNAME] } {
-	set _CHIPNAME $CHIPNAME
-} else {
-	set _CHIPNAME esp32
-}
-
-if { [info exists CPUTAPID] } {
-	set _CPUTAPID $CPUTAPID
-} else {
-	set _CPUTAPID 0x120034e5
-}
+# Target specific global variables
+set _CHIPNAME 					"esp32"
+set _CPUTAPID 					0x120034e5
+set _ESP_ARCH 					"xtensa"
+set _ONLYCPU					3
+set _FLASH_VOLTAGE 				3.3
+set _ESP_SMP_TARGET				1
+set _ESP_SMP_BREAK 				1
+set _ESP_EFUSE_MAC_ADDR_REG 	0x3ff5A004
 
 if { [info exists ESP32_ONLYCPU] } {
 	set _ONLYCPU $ESP32_ONLYCPU
-} else {
-	set _ONLYCPU 2
 }
 
 if { [info exists ESP32_FLASH_VOLTAGE] } {
 	set _FLASH_VOLTAGE $ESP32_FLASH_VOLTAGE
-} else {
-	set _FLASH_VOLTAGE 3.3
-}
-
-set _CPU0NAME cpu0
-set _CPU1NAME cpu1
-set _TARGETNAME_0 $_CHIPNAME.$_CPU0NAME
-set _TARGETNAME_1 $_CHIPNAME.$_CPU1NAME
-
-jtag newtap $_CHIPNAME $_CPU0NAME -irlen 5 -expected-id $_CPUTAPID
-if { $_ONLYCPU != 1 } {
-	jtag newtap $_CHIPNAME $_CPU1NAME -irlen 5 -expected-id $_CPUTAPID
-} else {
-	jtag newtap $_CHIPNAME $_CPU1NAME -irlen 5 -disable -expected-id $_CPUTAPID
-}
-
-# PRO-CPU
-target create $_TARGETNAME_0 $_CHIPNAME -endian little -chain-position $_TARGETNAME_0 -coreid 0
-# APP-CPU
-if { $_ONLYCPU != 1 } {
-	target create $_TARGETNAME_1 $_CHIPNAME -endian little -chain-position $_TARGETNAME_1 -coreid 1
-	target smp $_TARGETNAME_0 $_TARGETNAME_1
-}
-
-$_TARGETNAME_0 esp32 flashbootstrap $_FLASH_VOLTAGE
-$_TARGETNAME_0 xtensa maskisr on
-$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
-$_TARGETNAME_0 configure -event reset-assert-post { soft_reset_halt }
-
-$_TARGETNAME_0 configure -event gdb-attach {
-	$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
-	# necessary to auto-probe flash bank when GDB is connected
-	halt 1000
-}
-
-if { $_ONLYCPU != 1 } {
-	$_TARGETNAME_1 configure -event gdb-attach {
-		$_TARGETNAME_1 xtensa smpbreak BreakIn BreakOut
-		# necessary to auto-probe flash bank when GDB is connected
-		halt 1000
-	}
-	$_TARGETNAME_1 configure -event reset-assert-post { soft_reset_halt }
 }
 
-$_TARGETNAME_0 configure -event examine-end {
-    # Need to enable to set 'semihosting_basedir'
-    arm semihosting enable
-    arm semihosting_resexit enable
-    if { [info exists _SEMIHOST_BASEDIR] } {
-        if { $_SEMIHOST_BASEDIR != "" } {
-            arm semihosting_basedir $_SEMIHOST_BASEDIR
-        }
-    }
+proc esp32_memprot_is_enabled { } {
+	return 0
 }
 
-if { $_ONLYCPU != 1 } {
-	$_TARGETNAME_1 configure -event examine-end {
-		# Need to enable to set 'semihosting_basedir'
-		arm semihosting enable
-		arm semihosting_resexit enable
-		if { [info exists _SEMIHOST_BASEDIR] } {
-			if { $_SEMIHOST_BASEDIR != "" } {
-				arm semihosting_basedir $_SEMIHOST_BASEDIR
-			}
-		}
-	}
+proc esp32_soc_reset { } {
+	soft_reset_halt
 }
 
-gdb_breakpoint_override hard
+create_esp_target $_ESP_ARCH
 
 source [find target/xtensa-core-esp32.cfg]
-- 
cgit v1.1


From 93002a86cde9cf95a894bdc099b67d6379e22cd3 Mon Sep 17 00:00:00 2001
From: Erhan Kurubas <erhan.kurubas@espressif.com>
Date: Sun, 18 Jun 2023 11:18:31 +0200
Subject: tcl/target: update esp32s2.cfg to reference shared functions in the
 esp_common.cfg

This commit enhances code reusability, simplifies maintenance, and ensures
consistency across all chip configurations by consolidating commonly used
commands and variables into the common config file.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I36c86fe4ebc99928ce48a5bff8cb9580a0fa3ac0
Reviewed-on: https://review.openocd.org/c/openocd/+/7746
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
---
 tcl/target/esp32s2.cfg | 62 ++++++++++----------------------------------------
 1 file changed, 12 insertions(+), 50 deletions(-)

(limited to 'tcl')

diff --git a/tcl/target/esp32s2.cfg b/tcl/target/esp32s2.cfg
index e478a6d..4c1362a 100644
--- a/tcl/target/esp32s2.cfg
+++ b/tcl/target/esp32s2.cfg
@@ -1,32 +1,17 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 #
-# The ESP32-S2 only supports JTAG.
-transport select jtag
 
-set CPU_MAX_ADDRESS 0xFFFFFFFF
-source [find bitsbytes.tcl]
-source [find memory.tcl]
-source [find mmr_helpers.tcl]
-# Source the ESP common configuration file
+# Source the ESP common configuration file.
 source [find target/esp_common.cfg]
 
-if { [info exists CHIPNAME] } {
-	set _CHIPNAME $CHIPNAME
-} else {
-	set _CHIPNAME esp32s2
-}
-
-if { [info exists CPUTAPID] } {
-	set _CPUTAPID $CPUTAPID
-} else {
-	set _CPUTAPID 0x120034e5
-}
-
-set _TARGETNAME $_CHIPNAME
-set _CPUNAME cpu
-set _TAPNAME $_CHIPNAME.$_CPUNAME
-
-jtag newtap $_CHIPNAME $_CPUNAME -irlen 5 -expected-id $_CPUTAPID
+# Target specific global variables
+set _CHIPNAME 					"esp32s2"
+set _CPUTAPID 					0x120034e5
+set _ESP_ARCH					"xtensa"
+set _ONLYCPU					1
+set _ESP_SMP_TARGET				0
+set _ESP_SMP_BREAK 				1
+set _ESP_EFUSE_MAC_ADDR_REG  	0x3f41A004
 
 proc esp32s2_memprot_is_enabled { } {
 	# IRAM0, DPORT_PMS_PRO_IRAM0_0_REG
@@ -48,33 +33,10 @@ proc esp32s2_memprot_is_enabled { } {
 	return 0
 }
 
-target create $_TARGETNAME esp32s2 -endian little -chain-position $_TAPNAME
-
-$_TARGETNAME configure -event gdb-attach {
-	# necessary to auto-probe flash bank when GDB is connected and generate proper memory map
-	halt 1000
-	if { [esp32s2_memprot_is_enabled] } {
-		# 'reset halt' to disable memory protection and allow flasher to work correctly
-		echo "Memory protection is enabled. Reset target to disable it..."
-		reset halt
-	}
-}
-
-xtensa maskisr on
-
-$_TARGETNAME configure -event examine-end {
-	# Need to enable to set 'semihosting_basedir'
-	arm semihosting enable
-	arm semihosting_resexit enable
-	if { [info exists _SEMIHOST_BASEDIR] } {
-		if { $_SEMIHOST_BASEDIR != "" } {
-			arm semihosting_basedir $_SEMIHOST_BASEDIR
-		}
-	}
+proc esp32s2_soc_reset { } {
+	soft_reset_halt
 }
 
-$_TARGETNAME configure -event reset-assert-post { soft_reset_halt }
-
-gdb_breakpoint_override hard
+create_esp_target $_ESP_ARCH
 
 source [find target/xtensa-core-esp32s2.cfg]
-- 
cgit v1.1


From 78daf24a5c29664669bb1d9d7851cbbb90dbc444 Mon Sep 17 00:00:00 2001
From: Erhan Kurubas <erhan.kurubas@espressif.com>
Date: Sun, 18 Jun 2023 11:00:22 +0200
Subject: tcl/target: update esp32s3.cfg to reference shared functions in the
 esp_common.cfg

This commit enhances code reusability, simplifies maintenance, and ensures
consistency across all chip configurations by consolidating commonly used
commands and variables into the common config file.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Ifb0122f3b98a767f27746409499733b70fb7d0e8
Reviewed-on: https://review.openocd.org/c/openocd/+/7747
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
---
 tcl/target/esp32s3.cfg | 104 ++++++-------------------------------------------
 1 file changed, 12 insertions(+), 92 deletions(-)

(limited to 'tcl')

diff --git a/tcl/target/esp32s3.cfg b/tcl/target/esp32s3.cfg
index 42b2199..12c166c 100644
--- a/tcl/target/esp32s3.cfg
+++ b/tcl/target/esp32s3.cfg
@@ -1,44 +1,20 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 #
-# The ESP32-S3 only supports JTAG.
-transport select jtag
 
-set CPU_MAX_ADDRESS 0xFFFFFFFF
-source [find bitsbytes.tcl]
-source [find memory.tcl]
-source [find mmr_helpers.tcl]
-# Source the ESP common configuration file
+# Source the ESP common configuration file.
 source [find target/esp_common.cfg]
 
-
-if { [info exists CHIPNAME] } {
-	set _CHIPNAME $CHIPNAME
-} else {
-	set _CHIPNAME esp32s3
-}
-
-if { [info exists CPUTAPID] } {
-	set _CPUTAPID $CPUTAPID
-} else {
-	set _CPUTAPID 0x120034e5
-}
+# Target specific global variables
+set _CHIPNAME 					"esp32s3"
+set _CPUTAPID 					0x120034e5
+set _ESP_ARCH 					"xtensa"
+set _ONLYCPU					3
+set _ESP_SMP_TARGET				1
+set _ESP_SMP_BREAK 				1
+set _ESP_EFUSE_MAC_ADDR_REG  	0x60007044
 
 if { [info exists ESP32_S3_ONLYCPU] } {
 	set _ONLYCPU $ESP32_S3_ONLYCPU
-} else {
-	set _ONLYCPU 2
-}
-
-set _CPU0NAME cpu0
-set _CPU1NAME cpu1
-set _TARGETNAME_0 $_CHIPNAME.$_CPU0NAME
-set _TARGETNAME_1 $_CHIPNAME.$_CPU1NAME
-
-jtag newtap $_CHIPNAME $_CPU0NAME -irlen 5 -expected-id $_CPUTAPID
-if { $_ONLYCPU != 1 } {
-	jtag newtap $_CHIPNAME $_CPU1NAME -irlen 5 -expected-id $_CPUTAPID
-} else {
-	jtag newtap $_CHIPNAME $_CPU1NAME -irlen 5 -disable -expected-id $_CPUTAPID
 }
 
 proc esp32s3_memprot_is_enabled { } {
@@ -89,66 +65,10 @@ proc esp32s3_memprot_is_enabled { } {
 	return 0
 }
 
-# PRO-CPU
-target create $_TARGETNAME_0 $_CHIPNAME -endian little -chain-position $_TARGETNAME_0 -coreid 0
-# APP-CPU
-if { $_ONLYCPU != 1 } {
-	target create $_TARGETNAME_1 $_CHIPNAME -endian little -chain-position $_TARGETNAME_1 -coreid 1
-	target smp $_TARGETNAME_0 $_TARGETNAME_1
-}
-
-$_TARGETNAME_0 xtensa maskisr on
-$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
-$_TARGETNAME_0 configure -event examine-end {
-	# Need to enable to set 'semihosting_basedir'
-	arm semihosting enable
-	arm semihosting_resexit enable
-	if { [info exists _SEMIHOST_BASEDIR] } {
-		if { $_SEMIHOST_BASEDIR != "" } {
-			arm semihosting_basedir $_SEMIHOST_BASEDIR
-		}
-	}
-}
-
-if { $_ONLYCPU != 1 } {
-	$_TARGETNAME_1 configure -event examine-end {
-		# Need to enable to set 'semihosting_basedir'
-		arm semihosting enable
-		arm semihosting_resexit enable
-		if { [info exists _SEMIHOST_BASEDIR] } {
-			if { $_SEMIHOST_BASEDIR != "" } {
-				arm semihosting_basedir $_SEMIHOST_BASEDIR
-			}
-		}
-	}
-}
-
-$_TARGETNAME_0 configure -event gdb-attach {
-	$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
-	# necessary to auto-probe flash bank when GDB is connected and generate proper memory map
-	halt 1000
-	if { [esp32s3_memprot_is_enabled] } {
-		# 'reset halt' to disable memory protection and allow flasher to work correctly
-		echo "Memory protection is enabled. Reset target to disable it..."
-		reset halt
-	}
-}
-$_TARGETNAME_0 configure -event reset-assert-post { soft_reset_halt }
-
-if { $_ONLYCPU != 1 } {
-	$_TARGETNAME_1 configure -event gdb-attach {
-		$_TARGETNAME_1 xtensa smpbreak BreakIn BreakOut
-		# necessary to auto-probe flash bank when GDB is connected
-		halt 1000
-		if { [esp32s3_memprot_is_enabled] } {
-			# 'reset halt' to disable memory protection and allow flasher to work correctly
-			echo "Memory protection is enabled. Reset target to disable it..."
-			reset halt
-		}
-	}
-	$_TARGETNAME_1 configure -event reset-assert-post { soft_reset_halt }
+proc esp32s3_soc_reset { } {
+	soft_reset_halt
 }
 
-gdb_breakpoint_override hard
+create_esp_target $_ESP_ARCH
 
 source [find target/xtensa-core-esp32s3.cfg]
-- 
cgit v1.1


From 1107af09f1179241224ff0045441caaeeec70b13 Mon Sep 17 00:00:00 2001
From: Erhan Kurubas <erhan.kurubas@espressif.com>
Date: Sun, 18 Jun 2023 12:59:19 +0200
Subject: tcl/interface: add Espressif builtin usb_jtag config file.

This config file enables communication over USB-JTAG with
ESP32-C3, ESP32-S3, ESP32-H2 and ESP32-C6 chips

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Iceea26972588d8c4919d1f3248684ece48ca9121
Reviewed-on: https://review.openocd.org/c/openocd/+/7748
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
---
 tcl/interface/esp_usb_jtag.cfg | 9 +++++++++
 1 file changed, 9 insertions(+)
 create mode 100644 tcl/interface/esp_usb_jtag.cfg

(limited to 'tcl')

diff --git a/tcl/interface/esp_usb_jtag.cfg b/tcl/interface/esp_usb_jtag.cfg
new file mode 100644
index 0000000..40427d0
--- /dev/null
+++ b/tcl/interface/esp_usb_jtag.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Espressif builtin USB-JTAG adapter
+#
+
+adapter driver esp_usb_jtag
+
+espusbjtag vid_pid 0x303a 0x1001
+espusbjtag caps_descriptor 0x2000
-- 
cgit v1.1


From 2c57d11c78108c6547f31ca07f1ff672fa855f10 Mon Sep 17 00:00:00 2001
From: Erhan Kurubas <erhan.kurubas@espressif.com>
Date: Sun, 18 Jun 2023 13:05:35 +0200
Subject: tcl/board: add esp32s3-builtin.cfg file

Board config file for ESP32-S3, to allow communication with
the builtin USB-JTAG adapter.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I1310f5db30f7df38fe9344f7ba2334611b53863e
Reviewed-on: https://review.openocd.org/c/openocd/+/7749
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
---
 tcl/board/esp32s3-builtin.cfg | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
 create mode 100644 tcl/board/esp32s3-builtin.cfg

(limited to 'tcl')

diff --git a/tcl/board/esp32s3-builtin.cfg b/tcl/board/esp32s3-builtin.cfg
new file mode 100644
index 0000000..353099c
--- /dev/null
+++ b/tcl/board/esp32s3-builtin.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Example OpenOCD configuration file for ESP32-S3 connected via builtin USB-JTAG adapter.
+#
+# For example, OpenOCD can be started for ESP32-S3 debugging on
+#
+#   openocd -f board/esp32s3-builtin.cfg
+#
+
+# Source the JTAG interface configuration file
+source [find interface/esp_usb_jtag.cfg]
+# Source the ESP32-S3 configuration file
+source [find target/esp32s3.cfg]
+
+adapter speed 40000
-- 
cgit v1.1


From 94686eea6e982a83e5c1796e8a903bf683ed62e5 Mon Sep 17 00:00:00 2001
From: Ahmed BOUDJELIDA <aboudjelida@nanoxplore.com>
Date: Sat, 17 Jun 2023 01:11:15 +0200
Subject: jtag/drivers: Add new driver for ANGIE USB-JTAG Adapter

This is the driver code for NanoXplore's ANGIE USB-JTAG Adapter.
The driver is based on the openULINK project.

This driver communicate with ANGIE's firmware in order to establish
JTAG protocol to debug the target chip.

Since the ANGIE Adapter has a Spartan-6 FPGA in addition to the
FX2 microcontroller, the driver adds two functions, one to download
the firmware (embedded C) to the FX2, and the second to program
the FPGA with its bitstream.

Add ANGIE's configuration file to tcl/interface/
Add the device VID/PID to 60-openocd.rules file.
Add ANGIE to OpenOCD's documentation

Change-Id: Id17111c74073da01450d43d466e11b0cc086691f
Signed-off-by: Ahmed BOUDJELIDA <aboudjelida@nanoxplore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7702
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
---
 tcl/interface/angie.cfg | 9 +++++++++
 1 file changed, 9 insertions(+)
 create mode 100644 tcl/interface/angie.cfg

(limited to 'tcl')

diff --git a/tcl/interface/angie.cfg b/tcl/interface/angie.cfg
new file mode 100644
index 0000000..26cbe39
--- /dev/null
+++ b/tcl/interface/angie.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (C) 2023 by NanoXplore, France - all rights reserved
+#
+# configuration file for ANGIE Adapter from NanoXplore.
+#
+
+adapter driver angie
+adapter speed 10000
+reset_config trst_and_srst trst_push_pull srst_open_drain
-- 
cgit v1.1


From 8774fd60177623051388bf7371c79ae7bb91a52d Mon Sep 17 00:00:00 2001
From: gudvinr <gudvinr@gmail.com>
Date: Thu, 27 Jul 2023 15:03:57 +0300
Subject: tcl/interface/ftdi: support for SIPEED RV-Debugger

BL702-based JTAG debugger that emulates FT2232D device

Change-Id: Iefbf03645e6d8d154f4b1cad3385b8bc09da37dd
Signed-off-by: gudvinr <gudvinr@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7830
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
---
 tcl/interface/ftdi/sipeed-rv-debugger.cfg | 13 +++++++++++++
 1 file changed, 13 insertions(+)
 create mode 100644 tcl/interface/ftdi/sipeed-rv-debugger.cfg

(limited to 'tcl')

diff --git a/tcl/interface/ftdi/sipeed-rv-debugger.cfg b/tcl/interface/ftdi/sipeed-rv-debugger.cfg
new file mode 100644
index 0000000..ca65398
--- /dev/null
+++ b/tcl/interface/ftdi/sipeed-rv-debugger.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Interface file for BL702-based SIPEED RV Debugger
+#
+
+adapter driver ftdi
+adapter speed 6000
+
+ftdi device_desc "JTAG Debugger"
+ftdi vid_pid 0x0403 0x6010
+ftdi layout_init 0x0008 0x001b
+ftdi layout_signal nSRST -oe 0x0020 -data 0x0020
-- 
cgit v1.1


From 3c558fda4bf09b5fd612f05a86da7ad5c47630bb Mon Sep 17 00:00:00 2001
From: Artemiy Volkov <artemiy@synopsys.com>
Date: Mon, 17 Jul 2023 17:07:28 +0200
Subject: tcl: add configuration files for the ARC HSDK-4xD board

This commit provides startup files for the Synopsys DesignWare ARC
HSDK-4xD board. These have been adapted from the corresponding
snps_hsdk.cfg files, the only functional change being the JTAG IDs for
the new board's CPU cores.

Change-Id: I19a0cd13bc09de90cfe2a7cccf1239e459fd8077
Signed-off-by: Artemiy Volkov <artemiy@synopsys.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7829
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Evgeniy Didin <didin@synopsys.com>
---
 tcl/board/snps_hsdk_4xd.cfg  | 19 +++++++++++++++++
 tcl/target/snps_hsdk_4xd.cfg | 50 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 69 insertions(+)
 create mode 100644 tcl/board/snps_hsdk_4xd.cfg
 create mode 100644 tcl/target/snps_hsdk_4xd.cfg

(limited to 'tcl')

diff --git a/tcl/board/snps_hsdk_4xd.cfg b/tcl/board/snps_hsdk_4xd.cfg
new file mode 100644
index 0000000..5901533
--- /dev/null
+++ b/tcl/board/snps_hsdk_4xd.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Copyright (C) 2023 Synopsys, Inc.
+# Artemiy Volkov <artemiy@synopsys.com>
+
+# Adapted from tcl/board/snps_hsdk.cfg.
+
+#
+# Synopsys DesignWare ARC HSDK Software Development Platform (HS47D cores)
+#
+
+source [find interface/ftdi/snps_sdp.cfg]
+adapter speed 10000
+
+# ARCs supports only JTAG.
+transport select jtag
+
+# Configure SoC
+source [find target/snps_hsdk_4xd.cfg]
diff --git a/tcl/target/snps_hsdk_4xd.cfg b/tcl/target/snps_hsdk_4xd.cfg
new file mode 100644
index 0000000..1520e3d
--- /dev/null
+++ b/tcl/target/snps_hsdk_4xd.cfg
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Copyright (C) 2023 Synopsys, Inc.
+# Artemiy Volkov <artemiy@synopsys.com>
+
+# Adapted from tcl/target/snps_hsdk.cfg.
+
+#
+# HS Development Kit SoC.
+#
+# Contains quad-core ARC HS47D.
+#
+
+source [find cpu/arc/hs.tcl]
+
+set _coreid 0
+set _dbgbase [expr {$_coreid << 13}]
+
+# CHIPNAME will be used to choose core family (600, 700 or EM). As far as
+# OpenOCD is concerned EM and HS are identical.
+set _CHIPNAME arc-em
+
+
+proc setup_cpu {core_index expected_id} {
+	global _coreid
+	global _dbgbase
+	global _CHIPNAME
+
+	set _TARGETNAME $_CHIPNAME.cpu$core_index
+	jtag newtap $_CHIPNAME cpu$core_index -irlen 4 -ircapture 0x1 -expected-id $expected_id
+
+	target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
+	$_TARGETNAME configure -coreid $_coreid
+	$_TARGETNAME configure -dbgbase $_dbgbase
+	$_TARGETNAME configure -event reset-assert "arc_hs_reset $_TARGETNAME"
+
+	arc_hs_init_regs
+
+	$_TARGETNAME arc cache l2 auto 1
+
+	set _coreid [expr {$_coreid + 1}]
+	set _dbgbase [expr {$_coreid << 13}]
+}
+
+# OpenOCD discovers JTAG TAPs in reverse order.
+
+setup_cpu 4 0x100c54b1
+setup_cpu 3 0x100854b1
+setup_cpu 2 0x100454b1
+setup_cpu 1 0x100054b1
-- 
cgit v1.1