From f4950b7c5d4a3ead9b1433c4ea6f3bbf3a540f9c Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Fri, 11 Jun 2021 13:01:55 -0700 Subject: From upstream (#620) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * cortex_m: use unsigned int for FPB and DWT quantifiers related quantifiers are: - fp_num_lit - fp_num_code - dwt_num_comp - dwt_comp_available Change-Id: I07dec2d4aa21bc0e580be0d9fd0a6809f876c2a8 Signed-off-by: Tarek BOCHKATI Reviewed-on: http://openocd.zylin.com/6185 Tested-by: jenkins Reviewed-by: Tomas Vanek * telnet: allow hiding selected commands during auto-completion We have TCL procedure and commands that we do not want to show in the list of auto-completion. E.g. TCL wrappers for deprecated commands, internal procedures that are not supposed to be exposed to user, or even commands that the user decides to hide. Create a TCL procedure to be called by telnet auto-complete code in place of the hard-coded TCL command. The procedure will run the same command and will filter-out the unwanted command names. Initialize the list of commands to be filtered-out with the name of the TCL procedure above, as it is considered as internal. Change-Id: I2d83bbf8194502368c589c85cccb617e69128c69 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6194 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI * telnet/auto-complete: hide deprecated and internal commands For both: - TCL proc that redirect deprecated commands to the new commands, - TCL proc used internally and not supposed to be exposed to user, add their name to the list of commands that should be hide by the telnet auto-complete. Change-Id: I05237c6a79334b7d2b151dfb129fb57b2f40bba6 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6195 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI * startup.tcl: prepare for jimtcl 0.81 'expr' syntax change Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single arg") drops the support for multi-argument syntax for the TCL command 'expr'. Modify the script startup.tcl compiled-in OpenOCD binary to comply with the new jimtcl. Change-Id: I520dcafacadaa289a815035f93f250447ca66ea0 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6158 Tested-by: jenkins Reviewed-by: Oleksij Rempel Reviewed-by: Tomas Vanek * tcl: [1/3] prepare for jimtcl 0.81 'expr' syntax change Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single arg") drops the support for multi-argument syntax for the TCL command 'expr'. In the TCL scripts distributed with OpenOCD there are 1700+ lines that should be modified before switching to jimtcl 0.81. Apply the script below on every script in tcl folder. It fixes more than 92% of the lines %<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<--- #!/usr/bin/perl -Wpi my $re_sym = qr{[a-z_][a-z0-9_]*}i; my $re_var = qr{(?:\$|\$::)$re_sym}; my $re_const = qr{0x[0-9a-f]+|[0-9]+|[0-9]*\.[0-9]*}i; my $re_item = qr{(?:~\s*)?(?:$re_var|$re_const)}; my $re_op = qr{<<|>>|[+\-*/&|]}; my $re_expr = qr{( (?:\(\s*(?:$re_item|(?-1))\s*\)|$re_item) \s*$re_op\s* (?:$re_item|(?-1)|\(\s*(?:$re_item|(?-1))\s*\)) )}x; # [expr [dict get $regsC100 SYM] + HEXNUM] s/\[expr (\[dict get $re_var $re_sym\s*\] \+ *$re_const)\]/\[expr \{$1\}\]/; # [ expr (EXPR) ] # [ expr EXPR ] # note: $re_expr captures '$3' s/\[(\s*expr\s*)\((\s*$re_expr\s*)\)(\s*)\]/\[$1\{$2\}$4\]/; s/\[(\s*expr\s*)($re_expr)(\s*)\]/\[$1\{$2\}$4\]/; %<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<--- Change-Id: I0d6bddc6abf6dd29062f2b4e72b5a2b5080293b9 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6159 Tested-by: jenkins Reviewed-by: Tomas Vanek * tcl: [2/3] prepare for jimtcl 0.81 'expr' syntax change Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single arg") drops the support for multi-argument syntax for the TCL command 'expr'. Enclose within double quote the argument of 'expr' when there is the need to concatenate strings. Change-Id: Ic0ea990ed37337a7e6c3a99670583685b570b8b1 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6160 Tested-by: jenkins * tcl: [3/3] prepare for jimtcl 0.81 'expr' syntax change Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single arg") drops the support for multi-argument syntax for the TCL command 'expr'. Fix manually the remaining lines that don't match simple patterns and would require dedicated boring scripting. Remove the 'expr' command where appropriate. Change-Id: Ia75210c8447f88d38515addab4a836af9103096d Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6161 Tested-by: jenkins Reviewed-by: Tomas Vanek * target/stm8: Make 'stm8_command_handlers' static Change-Id: I5237a8f2a1ecba9383672e37bd56f8ccd17598b6 Signed-off-by: Marc Schink Reviewed-on: http://openocd.zylin.com/6200 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI Reviewed-by: Antonio Borneo * target/riscv: Change 'authdata_read' output Use a constant output length and remove the line break to make the authentication data easier to parse. Change-Id: Iebbf1f171947ef89b0f360a2cb286a4ea15c6ba5 Signed-off-by: Marc Schink Reviewed-on: http://openocd.zylin.com/6199 Tested-by: jenkins Reviewed-by: Antonio Borneo Reviewed-by: Tim Newsome * Enable adapter "Bus Pirate" by default. The Bus Pirate is now listed in the "OpenOCD configuration summary" too. Change-Id: Ieb7bf9134af456ebe9803f3108a243204fb2a62d Signed-off-by: R. Diez Reviewed-on: http://openocd.zylin.com/5637 Tested-by: jenkins Reviewed-by: Antonio Borneo * coding-style: additional style for C code To improve readability and to push more uniform code style. Prefer 'if (false) {...}' for unused code so it get checked by the compiler. Define preferred indentation for 'switch' statement. Require balanced brackets in 'if/else'. Report the max line length. Report the formatting strings for stdint/inttypes types. Report the type 'target_addr_t'. Prefer 'unsigned int' to 'unsigned'. Change-Id: I0192a4ed298f6c6c432764fdd156cffd4b13fc89 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6203 Reviewed-by: Tomas Vanek Tested-by: jenkins Reviewed-by: Oleksij Rempel Reviewed-by: Tarek BOCHKATI Reviewed-by: Marc Schink * Add IPDBG JtagHost functionality to OpenOCD IPDBG are utilities to debug IP-cores. It uses JTAG for transport to/from the FPGA. The different UIs use TCP/IP as transport. The JtagHost makes the bridge between these two. Comparable to the bridge between GDB and the in-circuit- debugging-unit of a micro controller. Change-Id: Ib1bc10dcbd4ea426e492bb7b2d85c1ed1b7a8d5a Signed-off-by: Daniel Anselmi Reviewed-on: http://openocd.zylin.com/5938 Tested-by: jenkins Reviewed-by: Antonio Borneo * flash/nor/xcf: Do not use 'Yoda conditions' Change-Id: I17308f5237338ce468e5b86289a0634429deaaa9 Signed-off-by: Marc Schink Reviewed-on: http://openocd.zylin.com/6201 Tested-by: jenkins Reviewed-by: Tomas Vanek Reviewed-by: Antonio Borneo * cortex_m: add armv8m special registers Change-Id: I1942f375a5f4282ad1fe4a2ff3b8f3cbc64d8f7f Signed-off-by: Tarek BOCHKATI Reviewed-on: http://openocd.zylin.com/6016 Tested-by: jenkins Reviewed-by: Tomas Vanek * rtos: Add support for Zephyr RTOS With this patch, the Zephyr[1] RTOS is supported by OpenOCD. As usual with support for other RTOSes, Zephyr must be compiled with the DEBUG_THREAD_INFO option. This will generate some symbols with information needed in order to build the list of threads. The current implementation is limited to Zephyr running on ARM Cortex-M processors. This is the only ARM variant supported by Zephyr at the moment and is used on most of the officially supported boards. [1] https://www.zephyrproject.org/ Change-Id: I22afdbec91562f3a22cf5b88cd4ea3a7a59ba0b4 Signed-off-by: Evgeniy Didin Signed-off-by: Leandro Pereira Signed-off-by: Daniel Glöckner Reviewed-on: http://openocd.zylin.com/4988 Tested-by: jenkins Reviewed-by: Oleksij Rempel Reviewed-by: Antonio Borneo * target/armv7m.h: [style] replace tab with space between variable type and name Change-Id: I9740c25857295a2a655d3046322a3f23f0ee7f78 Signed-off-by: Tarek BOCHKATI Reviewed-on: http://openocd.zylin.com/6230 Reviewed-by: Marc Schink Tested-by: jenkins Reviewed-by: Antonio Borneo * server: gdb_server: Add colon for target extended-remote Both GDB commands "target remote" and "target extended-remote" require to have ":" right before port number. e.g. (gdb) target extended-remote :3333 Add ":" to the warning message so that users can copy & past it. Change-Id: Id6d8ec1e4dfd3c12cb7f3b314064f2c35fa7ab55 Signed-off-by: Yasushi SHOJI Reviewed-on: http://openocd.zylin.com/6237 Reviewed-by: Tarek BOCHKATI Tested-by: jenkins Reviewed-by: Marc Schink Reviewed-by: Antonio Borneo * jimtcl: restrict memory leak workaround on Linux only The workaround for jimtcl 0.80 in commit 36ae487ed04b ("jimtcl: add temporary workaround for memory leak in jimtcl 0.80") issues a compile time error on macOS: ../src/helper/command.c:157:22: error: aliases are not supported on darwin __attribute__((weak, alias("workaround_createcommand"))); The OS is x86_64-apple-darwin19.6.0 and the compiler used is x86_64-apple-darwin13.4.0-clang. Restrict the workaround on Linux host only. The fix for 'expr' syntax change is already merged and the workaround will be dropped soon. Change-Id: I925109a9c57c05f8c95b70bc7d6604eb1172cd79 Signed-off-by: Antonio Borneo Reported-by: Adam Jeliński Fixes: 36ae487ed04b ("jimtcl: add temporary workaround for memory leak in jimtcl 0.80") Fixes: https://sourceforge.net/p/openocd/tickets/304/ Reviewed-on: http://openocd.zylin.com/6241 Tested-by: jenkins * target/armv7m: fix static analyzer warning Despite of assert(is_packed) clang static analyser complains on use of the uninitialized offset variable. Cross compiling with latest x86_64-w64-mingw32-gcc hits warnings src/target/armv7m.c: In function ‘armv7m_read_core_reg’: src/target/armv7m.c:337:54: error: ‘reg32_id’ may be used uninitialized in this function [-Werror=maybe-uninitialized] It happens because mingw32 defines assert() without the attribute "noreturn", whatever NDEBUG is defined or not. Replace assert(is_packed) by if (is_packed) conditional and call assert(false) in the else branch. Change-Id: Id3c7dcccb65106e28be200b9a4d2b642f4d31019 Signed-off-by: Tomas Vanek Reviewed-on: http://openocd.zylin.com/6256 Tested-by: jenkins Reviewed-by: Antonio Borneo Reviewed-by: Tarek BOCHKATI Reviewed-by: Andrzej Sierżęga * cmsis_dap: fix build on macOS Compile fails with error: src/jtag/drivers/cmsis_dap.c:683:28: error: format specifies type 'unsigned char' but the argument has type 'int' [-Werror,-Wformat] " received 0x%" PRIx8, CMD_DAP_TFER, resp[0]); ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~ Fix the format specifier. Change-Id: I0a5a1a35452d634019989d14d849501fb8a7e93a Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6255 Tested-by: jenkins Reviewed-by: Tomas Vanek * cortex_m: do not perform soft_reset_halt on targets without VECTRESET Change-Id: Ib3df457e0afe4e342c82ad1af25e03aad6979d87 Signed-off-by: Tarek BOCHKATI Reviewed-on: http://openocd.zylin.com/6209 Tested-by: jenkins Reviewed-by: Antonio Borneo Reviewed-by: Tomas Vanek * cortex_m: fix VECTRESET detection for ARMv6-M cores VECTRESET check should be done after verifying if the core is an ARMv6-M core, and not before that. Fixes: 2dc9c1df81b6 ("cortex_m: [FIX] ARMv8-M does not support VECTRESET") Change-Id: I8306affd332b3a35cea69bba39ef24ca71244273 Signed-off-by: Tarek BOCHKATI Reviewed-on: http://openocd.zylin.com/6232 Tested-by: jenkins Reviewed-by: Tomas Vanek Reviewed-by: Antonio Borneo * target/arm_dpm: rename 'wp_pc' as 'wp_addr' The field 'wp_pc' was originally introduced in commit 55eeea7fceb6 ("ARMv7a/Cortex-A8: report watchpoint trigger insn") in end 2009 to contain the address of the instruction which triggered a watchpoint. Later on with commit 651b861d5d5f ("target/aarch64: Add watchpoint support") it has been reused in to hold directly the memory address that triggered a watchpoint. Rename 'wp_pc' as 'wp_addr' and change its doxygen description. While there, fix the format string to print the field. Change-Id: I2e5ced1497e4a6fb6b38f91e881807512e8d8c47 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6204 Tested-by: jenkins Reviewed-by: Liming Sun * target/aarch64: fix watchpoint management The early documentation for armv8a report the debug register WFAR as containing the address of the instruction that triggered the watchpoint. More recent documentation report the register EDWAR as containing the data memory address that triggered the watchpoint. The name of macros CPUV8_DBG_WFAR0 and CPUV8_DBG_WFAR1 is not correct as they point to the debug register EDWAR, so reading such register returns directly the data memory address that triggered the watchpoint. The code incorrectly passes this address value to the function armv8_dpm_report_wfar(); this function is supposed to adjust the PC value, decrementing it to remove the effects of the CPU pipeline. This pipeline offset, that has no meaning on the value in EDWAR, caused commit 651b861d5d5f ("target/aarch64: Add watchpoint support") to add back the offset while comparing the address with the watchpoint enabled. The upper 32 bits of EDWAR are not valid in aarch32 mode and have to be ignored. Rename CPUV8_DBG_WFAR0/1 as CPUV8_DBG_EDWAR0/1. Remove the function armv8_dpm_report_wfar(). Remove the offset while searching the matching watchpoint. Ignore the upper 32 bits of EDWAR in aarch32 mode. Fix a comment and the LOG text. Change-Id: I7cbdbeb766fa18e31cc72be098ca2bc501877ed1 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6205 Tested-by: jenkins Reviewed-by: Liming Sun * flash/stm32l4x: add missing break statement this is not a bug fix, this for loop will issue only one match adding the break will save unnecessary more loops. Change-Id: Ic1484ea8cdea1b284eb570f9e3e7818e07daf5cd Signed-off-by: Tarek BOCHKATI Reviewed-on: http://openocd.zylin.com/6248 Reviewed-by: Oleksij Rempel Tested-by: jenkins * github/action: create a permanent 'latest' release this commit extends the existing snapshot action to create a release named 'latest' with the built binaries for windows. this 'latest' release will be updated after every push to github. Change-Id: I75a64c598169241743add3ac9aa7a0337fbab7f2 Signed-off-by: Tarek BOCHKATI Reviewed-on: http://openocd.zylin.com/6127 Tested-by: jenkins Reviewed-by: Antonio Borneo * tcl/rp2040: remove empty line at end of file Change-Id: I212a96b77282b151a8ecbd46a6436e2bbbda4161 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6221 Tested-by: jenkins * tcl: fix some minor typo Minor typos found by the new checkpatch boosted by the dictionary provided by 'codespell'. While there, fix one indentation. Change-Id: I72369ed26f363bacd760b40b8c83dd95e89d28a4 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6214 Tested-by: jenkins * flash: fix some minor typo Minor typos found by the new checkpatch boosted by the dictionary provided by 'codespell'. Change-Id: Ia5f134c91beb483fd865df9e4877e0ec3e789478 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6215 Tested-by: jenkins * jtag: fix some minor typo Minor typos found by the new checkpatch boosted by the dictionary provided by 'codespell'. Change-Id: I101c76a638805d77c1ff356cf0f027552389e5d3 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6216 Tested-by: jenkins * target: fix some minor typo Minor typos found by the new checkpatch boosted by the dictionary provided by 'codespell'. Change-Id: I548581247db72e683249749d1b8725035530b06e Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6217 Tested-by: jenkins * openocd: fix some minor typo Minor typos found by the new checkpatch boosted by the dictionary provided by 'codespell'. Change-Id: I7b4cae1798ff5ea048fcbc671a397af763fdc605 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6218 Tested-by: jenkins * Document the buspirate interface driver. Change-Id: Iaff13fc5187041a840f4f00eb6b4ee52880cf47e Signed-off-by: R. Diez Reviewed-on: http://openocd.zylin.com/6231 Tested-by: jenkins Reviewed-by: Antonio Borneo * Warn on undefined preprocessor symbols Preprocessor directives like "#if SYMBOL" silently replace undefined or misspelt symbols with 0, which makes configuration bugs hard to spot. Compiler flag "-Wundef" prevents such errors. Change-Id: I91b7ba2db02ef0c3c452d334601c53aebda4660e Signed-off-by: R. Diez Reviewed-on: http://openocd.zylin.com/6238 Tested-by: jenkins Reviewed-by: Antonio Borneo * Remove compatibility macros m4_ifblank and m4_ifnblank They are at least since Autoconf 2.67 present, and we are requiring version 2.69. Change-Id: I41b33d4ebe02198f03cdddcc4a3c1beedd993d78 Signed-off-by: R. Diez Reviewed-on: http://openocd.zylin.com/6239 Tested-by: jenkins Reviewed-by: Antonio Borneo * configure.ac: use a separate folder for Autoconf-generated files Autoconf generates several files in root folder of the project. Keep the root folder cleaner by specifying subfolder 'build-aux'. Align .gitignore accordingly. Signed-off-by: R. Diez Change-Id: Ied87faba495d9eeb8f98e78c2e2b7e7e596febfb Reviewed-on: http://openocd.zylin.com/6236 Tested-by: jenkins Reviewed-by: Antonio Borneo * helper/command: silent debug msg on command register/unregister Commit e216186fab59 ("helper/command: register full-name commands in jim") and commit a7d68878e4ba ("helper/command: unregister commands through their full-name") introduce a LOG_DEBUG() message each for command registration and unregistration. The messages above are quite noisy and pollute the log when debug_level is 3 or higher. They can be useful to debug the command registration logic, but for the other debug activities on OpenOCD are just noisy. Already commit a03ac1ba3087 ("helper/command: disable logging of registered commands [RFC]") was merged to silent the first case that is now back with additional logs. Silent both log messages. Use 'if (false)' to silent them, making easy to re-enable it when or if someone needs it. Change-Id: Id8a067e60e822d4ecbddcb036d081298f7e6181f Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6220 Tested-by: jenkins * mem_ap: fix target arch_info type The target mem_ap appears as an ARM target, thus it allows the execution of ARM specific commands causing the crash of OpenOCD. E.g. 'arm mrc ...' can be executed and segfaults. Replace the incorrect ARM magic number with a dedicated one. While there, remove the 'struct arm', that is now holding only the mem_ap's dap, and replace it with a pointer to the dap. Change-Id: I881332d3fdf8d8f8271b8711607737b052a5699b Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6213 Tested-by: jenkins * riscv: drop unused variable The array newly_halted[] is assigned but its value is never used. Drop it! Change-Id: I678812a31c45a3ec03716e3eee6a30b8e8947926 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6257 Tested-by: jenkins Reviewed-by: Xiang W Reviewed-by: Tim Newsome * riscv: replace macro DIM() with ARRAY_SIZE() OpenOCD already defines the macro ARRAY_SIZE, while riscv code uses a local macro DIM. Prefer using the macro ARRAY_SIZE() instead of DIM(). Not all the riscv code has been upstreamed, yes; this patch only covers the code already upstreamed. Change-Id: I89a58a6d91916d85c53ba5e4091b558271f8d618 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6258 Reviewed-by: Xiang W Tested-by: jenkins Reviewed-by: Tim Newsome * target/zynqmp : Add AXI AP access port The Xilinx Zynq UltraScale+ SoC have an "AXI-AP" access port for direct memory accesses without halting CPUs. Change-Id: I6303331c217795657575de4759444938e775dee1 Signed-off-by: Olivier DANET Reviewed-on: http://openocd.zylin.com/6263 Reviewed-by: Tarek BOCHKATI Tested-by: jenkins Reviewed-by: Antonio Borneo * drivers/versaloon: use ARRAY_SIZE() Replace the custom macro dimof() with the OpenOCD macro ARRAY_SIZE(). Change-Id: I2fe638444f6c16f2a78c1fd558b21550f76282d6 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6259 Tested-by: jenkins Reviewed-by: Xiang W * openocd: use macro ARRAY_SIZE() There are still few cases where the macro ARRAY_SIZE() should be used in place of custom code. Use ARRAY_SIZE() whenever possible. Change-Id: Iba0127a02357bc704fe639e08562a4f9aa7011df Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6260 Reviewed-by: Xiang W Tested-by: jenkins * rtos: use ARRAY_SIZE() and simplify rtos_type.create() Use the existing macro ARRAY_SIZE(). Rewrite the functions rtos_type.create() to simplify the logic. Change-Id: I8833354767045d1642801d26944c9087a77add00 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6261 Tested-by: jenkins * tcl: remove remaining deprecated commands There are still few adapter_khz, ftdi_location, jtag_nsrst_delay and xds110_serial strolling around ... Change-Id: I3e8503dcc3875e3c92e6536f3d455a5e448d51ff Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6270 Tested-by: jenkins * help text: remove trailing space Some help text end with a useless space character. Remove it. Change-Id: I397e1194fac8042f0fab694222f925f906716de3 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6222 Tested-by: jenkins * help: fix line size in 'usage' output The implementation of command 'usage' is broken while checking the line limit of 76 chars per line (e.g. 'usage load_image') and the line wrapping is not correct. The same broken code is used for the first output line of command 'help' too. When call command_help_show_wrap(), include the command's name in the string so the whole text would be wrapped. Change-Id: Idece01ce54994db7e851d8522435ff764b11f3ac Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6223 Tested-by: jenkins * LICENSES: Add the MIT license Add the full text of the MIT license to the kernel tree. It was copied directly from: https://spdx.org/licenses/MIT.html#licenseText Add the required tags for reference and tooling. Change-Id: I94a5dea5ced6421809ea2a3448f8dda19a93f5c9 Signed-off-by: Thomas Gleixner Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6219 Tested-by: jenkins * stlink: add comment of firmware version for each flag bit Change-Id: I7f7c7b9c9cfd88125f82662ed864a2c0715140b1 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6211 Tested-by: jenkins * stlink: reorder the flag macro by firmware release The corresponding bit for each macro is changed, but this is not relevant in the code. Change-Id: I7039464f5a3d55d008208f44952aadeb815bd5a3 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6212 Tested-by: jenkins * tcl/board: Add ST NUCLEO-8S208RB Change-Id: I384c6ad9b4cbabbc004160677f600d8c4bd3eb71 Signed-off-by: Marc Schink Reviewed-on: http://openocd.zylin.com/6268 Tested-by: jenkins Reviewed-by: Antonio Borneo * target/arm_adi_v5: Fix clear sticky overrun flag during replay of commands When a WAIT occurs the commands after the WAIT are replayed and the STICKYORUN is cleared. However if another WAIT occurs during the command replay, the command itself is resent but the STICKYORUN bit shall also be cleared. If this is not done, the MEM-AP hangs. Change-Id: I14e8340cd5d8f58f4de31509da96cfa2ecb630d1 Signed-off-by: micbis Reviewed-on: http://openocd.zylin.com/6278 Tested-by: jenkins Reviewed-by: Matthias Welwarsky * target/cortex_a: add support for watchpoints The current implementation of OpenOCD does not support watchpoints for cortex_a architecture. So, I replaced the add_watchpoint and remove_watchpoint with the specific implementation for the cortex a and using the breakpoint implementation and the arm documentation [1] as reference. In particular, I have made the following changes: * added the following functions - cortex_a_add_watchpoint This wrapper function check whether there are any watchpoint available on the target device by calling cortex_a_set_watchpoint. - cortex_a_set_watchpoint This function is responsible for settings the watchpoint register pair. In particular, it sets the WVR and the WCR registers with the cortex_a_dap command. - cortex_a_remove_watchpoint This wrapper function the selected watchpoint on the target device by calling cortex_a_unset_watchpoint. - cortex_a_unset_watchpoint This function sets both the WVR and the WCR registers to zero, thus unsetting the watchpoint. [1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464f/BCGDHIEJ.html Change-Id: I86611dab474cb84836662af572b17636dc68e282 Signed-off-by: Chengyu Zheng Reviewed-on: http://openocd.zylin.com/3913 Reviewed-by: Antonio Borneo Reviewed-by: Matthias Welwarsky Reviewed-by: Marc Schink Tested-by: jenkins * target/cortex_a: fix number of watchpoints Decrement the available watchpoints only when succeed setting it. Initialize the available watchpoint with the correct value. Change-Id: I0f93b347300b8ebedbcd9e718d4ba32b26cf6846 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6196 Tested-by: jenkins Reviewed-by: Matthias Welwarsky * target/cortex_a: add support for watchpoint length of 1, 2 and 4 bytes Use byte address select for 1 and 2 bytes length. Use normal mode for 4 bytes length. Change-Id: I28d182f25145d0635de64d0361d456f1ad96640e Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6197 Tested-by: jenkins Reviewed-by: Matthias Welwarsky * target/cortex_a: fix memory leak on watchpoints The memory allocated to hold the watchpoints is not freed at OpenOCD exit. Free the watchpoint memory at OpenOCD exit. Change-Id: I518c9ce0dc901cde2913d752e3154734f878b854 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6210 Tested-by: jenkins Reviewed-by: Matthias Welwarsky * helper/jim-nvp: comply with coding style [1/2] The helper jim-nvp does not comply with OpenOCD coding style due to typedef of struct and CamelCase symbol names. While it's trivial fixing the helper and all its current use in the code, changing these APIs will potentially break a number of patches pending in gerrit. Gerrit will not trigger any alert, but the code will generate compile error after the merge. Add the compile flag "-Wno-error=deprecated-declarations" to keep as warning (not as error) the use of "deprecated" functions and types. Rename all the CamelCase symbols is lowercase and provide struct prototypes in place of the typedef. Add a DEPRECATED section to 'jim-nvp.h' where the old CamelCase symbols and the old typedef are re-declared with compile attribute 'deprecated'. With this change OpenOCD compiles, but generates warnings. The remaining changes allover OpenOCD code will be fixed in a separate patch for easier review. The patches merged later that still use the old deprecated API will compile with warnings. This will permit to identify and fix these cases. Change-Id: I786385d0f662dbb1be5be313ae42623156d68ce5 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6183 Tested-by: jenkins Reviewed-by: Marc Schink * helper/jim-nvp: comply with coding style [2/2] With the API fixed to comply with OpenOCD coding style, fix all the references in the code. Patch generated automatically with the script below. The list is in reverse order to replace a common prefix after the replacement of the symbols with the same prefix. %<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<--- (cat << EOF Jim_SetResult_NvpUnknown jim_set_result_nvp_unknown Jim_Nvp_value2name_simple jim_nvp_value2name_simple Jim_Nvp_value2name_obj jim_nvp_value2name_obj Jim_Nvp_value2name jim_nvp_value2name Jim_Nvp_name2value_simple jim_nvp_name2value_simple Jim_Nvp_name2value_obj_nocase jim_nvp_name2value_obj_nocase Jim_Nvp_name2value_obj jim_nvp_name2value_obj Jim_Nvp_name2value_nocase_simple jim_nvp_name2value_nocase_simple Jim_Nvp_name2value_nocase jim_nvp_name2value_nocase Jim_Nvp_name2value jim_nvp_name2value Jim_Nvp struct jim_nvp Jim_GetOpt_Wide jim_getopt_wide Jim_GetOpt_String jim_getopt_string Jim_GetOpt_Setup jim_getopt_setup Jim_GetOpt_Obj jim_getopt_obj Jim_GetOpt_NvpUnknown jim_getopt_nvp_unknown Jim_GetOpt_Nvp jim_getopt_nvp Jim_GetOpt_Enum jim_getopt_enum Jim_GetOpt_Double jim_getopt_double Jim_GetOpt_Debug jim_getopt_debug Jim_GetOptInfo struct jim_getopt_info Jim_GetNvp jim_get_nvp Jim_Debug_ArgvString jim_debug_argv_string EOF ) | while read a b; do sed -i "s/$a/$b/g" $(find src -type f ! -name jim-nvp.\? ) done %<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<--- Change-Id: I10a12bd64bb8b17575fd9150482c989c92b298a2 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6184 Reviewed-by: Marc Schink Tested-by: jenkins * server/telnet: fix autocomplete for jimtcl commands Current autocomplete filters-out some command reported by "info commands". One of the filter rule concerns the command's private data. Every command registered by OpenOCD has its 'struct command' as private data. By ignoring commands without private data, we loose several TCL commands registered by jimtcl, e.g. 'foreach', 'llength'. By assuming that every command with non-NULL private data has 'struct command' as private data, we risk at best to access inconsistent data, at worst to trigger a segmentation fault. Export the already available functions: - to check if a command has been registered by OpenOCD and - to get the private data. While there, rename jimcmd_is_ocd_command() as jimcmd_is_oocd_command(). Don't filter-out jimtcl commands with no private data. Check the private data only on OpenOCD commands. Change-Id: Ib5bf8d2bc5c12440c0cfae438f637c38724a79b7 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6282 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI * helper/list.h: align file to Linux v5.12 Main improvement is in the doxygen comments. Minimize the delta with kernel file. Skip the functions hlist_unhashed_lockless() and __list_del_clearprev() that are relevant only in kernel. Remove gcc extension "omitted conditional operand". Change-Id: I2e9ddb54cfe2fa5f7cf18f44726acd144e1f98b9 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6276 Reviewed-by: Tested-by: jenkins Reviewed-by: Andreas Fritiofson * contrib: add an example of using list.h Change-Id: Ic3d399d7ad2e4d10677cf78d64968040941b74e5 Signed-off-by: Andreas Fritiofson Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6280 Tested-by: jenkins Reviewed-by: Tim Newsome * helper/list.h: add mention to the example in contrib Without such reference, it could be difficult to find the example. Change-Id: Ia9ffb06bc1a45446c2c7b53197ab3400e1d8a9e9 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6281 Tested-by: jenkins Reviewed-by: Tim Newsome * tcl/target/stm32f4x: fix hardcoded chip name Fixes: c945d6e61605 ("tcl/target: start using the new TPIU/SWO support") Change-Id: I4543c9a204f7b4b3b14e6eabc5042653106aff0e Signed-off-by: Tarek BOCHKATI Reviewed-on: http://openocd.zylin.com/6277 Reviewed-by: Antonio Borneo Tested-by: jenkins * Makefile: add special target .DELETE_ON_ERROR The special .DELETE_ON_ERROR deletes the target file on recipe error. Otherwise, an incomplete output file may be considered up to date the next time around. .DELETE_ON_ERROR provides reasonable protection at virtually no cost. Signed-off-by: R. Diez Change-Id: I67dca47ae5ddf3786993c87b9991b3046a85f00b Reviewed-on: http://openocd.zylin.com/6235 Tested-by: jenkins Reviewed-by: Antonio Borneo * gdb_server: Log both incoming and outgoing GDB packets - Made sure that also outgoing GDB packets are logged, not only the incoming ones. - Improved the treatment of non-printable characters in the packets to make it more robust. Prior to this change: - Outgoing packets were not printed unless OpenOCD was re-compiled with _DEBUG_GDB_IO_. - Non-prinable characters were only treated in incoming 'X' packets. After this change: - Both incoming and outgoing GDB packets are logged on debug_level >= 3, so that both directions of the GDB channel are visible. - Non-printable characters are checked for in every packet so that hey do not interfere with the terminal. Change-Id: I0613e57ae5059b3279b0abcb71276cf5719a8699 Signed-off-by: Jan Matyas Reviewed-on: http://openocd.zylin.com/6269 Tested-by: jenkins Reviewed-by: Antonio Borneo * target/renesas_rz_g2: Introduce tcl config file for RZ/G2 devices Initial support for Renesas RZ/G2 MPU family Change-Id: I5ca74cddfd0c105a5307de56c3ade7084f9c28d2 Signed-off-by: micbis Reviewed-on: http://openocd.zylin.com/6250 Tested-by: jenkins Reviewed-by: Antonio Borneo * drivers/jlink: Remove trailing dots This makes the messages consistent with most of the rest of the OpenOCD output. Change-Id: I915a01187e7fc317e02483ac0bbd39ec077d6321 Signed-off-by: Marc Schink Reviewed-on: http://openocd.zylin.com/6274 Tested-by: jenkins Reviewed-by: Antonio Borneo * target: Use 'bool' for 'reset_halt' Change-Id: I974a6360ea7467067511541ac212f2e9d3de7895 Signed-off-by: Marc Schink Reviewed-on: http://openocd.zylin.com/6262 Tested-by: jenkins Reviewed-by: Antonio Borneo * cmsis_dap: add support for swo commands Replaced mixed snake_case_CamelCase with snake_case. Define variables at first-use location. CMSIS-DAP SWO specification: https://arm-software.github.io/CMSIS_5/DAP/html/group__DAP__swo__gr.html Change-Id: Ieba79b16efd445143f964b614673d041aae74f92 Signed-off-by: Adrian Negreanu Reviewed-on: http://openocd.zylin.com/5820 Tested-by: jenkins Reviewed-by: Antonio Borneo * Add target_data_bits(). This is used to compute memory block read alignment, and specifically allows 64-bit targets to ensure that memory block reads are only requested on 64-bit boundaries. Signed-off-by: Tim Newsome Change-Id: Idb1a27b9fc02c46245556bb0f3d6d94b368c4817 Reviewed-on: http://openocd.zylin.com/6249 Reviewed-by: Marc Schink Tested-by: jenkins Reviewed-by: Jan Matyas Reviewed-by: Xiang W Reviewed-by: Antonio Borneo * Avoid non-standard conditionals with omitted operands. Fixes bug #257. Change-Id: I05fc6468306d46399e769098e031e7e588798afc Signed-off-by: R. Diez Reviewed-on: http://openocd.zylin.com/6271 Tested-by: jenkins Reviewed-by: Xiang W Reviewed-by: Antonio Borneo * target/startup.tcl: Do not use 'Yoda conditions' Change-Id: I5e1bbaf032659dda1b365ef4ec6ea4a635d921ce Signed-off-by: Marc Schink Reviewed-on: http://openocd.zylin.com/6284 Tested-by: jenkins Reviewed-by: Antonio Borneo * Fix build. Change-Id: I4f2667db91f84f07af354691aac5d4c9e3aea3fa Signed-off-by: Tim Newsome Co-authored-by: Tarek BOCHKATI Co-authored-by: Antonio Borneo Co-authored-by: Marc Schink Co-authored-by: R. Diez Co-authored-by: Daniel Anselmi Co-authored-by: Evgeniy Didin Co-authored-by: Yasushi SHOJI Co-authored-by: Tomas Vanek Co-authored-by: Olivier DANET Co-authored-by: Thomas Gleixner Co-authored-by: micbis Co-authored-by: Chengyu Zheng Co-authored-by: Andreas Fritiofson Co-authored-by: Jan Matyas Co-authored-by: Adrian Negreanu --- tcl/target/am335x.cfg | 8 +- tcl/target/am437x.cfg | 918 ++++++++++++++++++++-------------------- tcl/target/ampere_emag.cfg | 2 +- tcl/target/bluenrg-x.cfg | 6 +- tcl/target/c100config.tcl | 50 +-- tcl/target/c100helper.tcl | 68 +-- tcl/target/c100regs.tcl | 386 ++++++++--------- tcl/target/davinci.cfg | 214 +++++----- tcl/target/fm4_mb9bf.cfg | 2 +- tcl/target/fm4_s6e2cc.cfg | 2 +- tcl/target/hilscher_netx500.cfg | 4 +- tcl/target/icepick.cfg | 6 +- tcl/target/imx.cfg | 2 +- tcl/target/ixp42x.cfg | 4 +- tcl/target/lpc8nxx.cfg | 2 +- tcl/target/omap4430.cfg | 2 +- tcl/target/omap4460.cfg | 2 +- tcl/target/or1k.cfg | 2 +- tcl/target/pic32mx.cfg | 2 +- tcl/target/psoc4.cfg | 14 +- tcl/target/psoc5lp.cfg | 8 +- tcl/target/renesas_rz_g2.cfg | 185 ++++++++ tcl/target/rp2040-core0.cfg | 1 - tcl/target/snps_em_sk_fpga.cfg | 2 +- tcl/target/snps_hsdk.cfg | 18 +- tcl/target/stellaris.cfg | 8 +- tcl/target/stm32f4x.cfg | 2 +- tcl/target/stm32h7x.cfg | 8 +- tcl/target/stm32mp15x.cfg | 2 +- tcl/target/ti_dm355.cfg | 2 +- tcl/target/ti_dm365.cfg | 2 +- tcl/target/u8500.cfg | 26 +- tcl/target/xilinx_zynqmp.cfg | 2 + 33 files changed, 1074 insertions(+), 888 deletions(-) create mode 100644 tcl/target/renesas_rz_g2.cfg (limited to 'tcl/target') diff --git a/tcl/target/am335x.cfg b/tcl/target/am335x.cfg index 02d8c7e..cb3e06c 100644 --- a/tcl/target/am335x.cfg +++ b/tcl/target/am335x.cfg @@ -85,8 +85,8 @@ $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x4000 # FIXME: unify with target/am437x.cfg source [find mem_helper.tcl] set WDT1_BASE_ADDR 0x44e35000 -set WDT1_W_PEND_WSPR [expr $WDT1_BASE_ADDR + 0x0034] -set WDT1_WSPR [expr $WDT1_BASE_ADDR + 0x0048] +set WDT1_W_PEND_WSPR [expr {$WDT1_BASE_ADDR + 0x0034}] +set WDT1_WSPR [expr {$WDT1_BASE_ADDR + 0x0048}] proc disable_watchdog { } { global WDT1_WSPR global WDT1_W_PEND_WSPR @@ -103,10 +103,10 @@ proc disable_watchdog { } { # Empty body to make sure this executes as fast as possible. # We don't want any delays here otherwise romcode might start # executing and end up changing state of certain IPs. - while { [expr [mrw $WDT1_W_PEND_WSPR] & 0x10] } { } + while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { } mww phys $WDT1_WSPR $WDT_DISABLE_SEQ2 - while { [expr [mrw $WDT1_W_PEND_WSPR] & 0x10] } { } + while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { } } } $_TARGETNAME configure -event reset-end { disable_watchdog } diff --git a/tcl/target/am437x.cfg b/tcl/target/am437x.cfg index 8ce0941..e954fd2 100644 --- a/tcl/target/am437x.cfg +++ b/tcl/target/am437x.cfg @@ -5,432 +5,432 @@ source [find mem_helper.tcl] ## AM437x Registers ## ############################################################################### set PRCM_BASE_ADDR 0x44df0000 -set REVISION_PRM [expr $PRCM_BASE_ADDR + 0x0000] -set PRM_IRQSTATUS_MPU [expr $PRCM_BASE_ADDR + 0x0004] -set PRM_IRQENABLE_MPU [expr $PRCM_BASE_ADDR + 0x0008] -set PRM_IRQSTATUS_M3 [expr $PRCM_BASE_ADDR + 0x000c] -set PRM_IRQENABLE_M3 [expr $PRCM_BASE_ADDR + 0x0010] -set PM_MPU_PWRSTCTRL [expr $PRCM_BASE_ADDR + 0x0300] -set PM_MPU_PWRSTST [expr $PRCM_BASE_ADDR + 0x0304] -set RM_MPU_RSTST [expr $PRCM_BASE_ADDR + 0x0314] -set RM_MPU_CONTEXT [expr $PRCM_BASE_ADDR + 0x0324] -set PM_GFX_PWRSTCTRL [expr $PRCM_BASE_ADDR + 0x0400] -set PM_GFX_PWRSTST [expr $PRCM_BASE_ADDR + 0x0404] -set RM_GFX_RSTCTRL [expr $PRCM_BASE_ADDR + 0x0410] -set RM_GFX_RSTST [expr $PRCM_BASE_ADDR + 0x0414] -set RM_GFX_CONTEXT [expr $PRCM_BASE_ADDR + 0x0424] -set RM_RTC_CONTEXT [expr $PRCM_BASE_ADDR + 0x0524] -set RM_WKUP_RSTCTRL [expr $PRCM_BASE_ADDR + 0x2010] -set RM_WKUP_RSTST [expr $PRCM_BASE_ADDR + 0x2014] -set CM_L3_AON_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x2800] -set CM_WKUP_DEBUGSS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2820] -set CM_L3S_TSC_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x2900] -set CM_WKUP_ADC_TSC_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2920] -set CM_L4_WKUP_AON_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x2a00] -set CM_WKUP_L4WKUP_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2a20] -set CM_WKUP_WKUP_M3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2a28] -set CM_WKUP_SYNCTIMER_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2a30] -set CM_WKUP_CLKDIV32K_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2a38] -set CM_WKUP_USBPHY0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2a40] -set CM_WKUP_USBPHY1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2a48] -set CM_WKUP_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x2b00] -set CM_WKUP_TIMER0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b20] -set CM_WKUP_TIMER1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b28] -set CM_WKUP_WDT0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b30] -set CM_WKUP_WDT1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b38] -set CM_WKUP_I2C0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b40] -set CM_WKUP_UART0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b48] -set CM_WKUP_SMARTREFLEX0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b50] -set CM_WKUP_SMARTREFLEX1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b58] -set CM_WKUP_CONTROL_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b60] -set CM_WKUP_GPIO0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b68] -set CM_CLKMODE_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d20] -set CM_IDLEST_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d24] -set CM_CLKSEL_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d2c] -set CM_DIV_M4_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d38] -set CM_DIV_M5_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d3c] -set CM_DIV_M6_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d40] -set CM_SSC_DELTAMSTEP_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d48] -set CM_SSC_MODFREQDIV_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d4c] -set CM_CLKMODE_DPLL_MPU [expr $PRCM_BASE_ADDR + 0x2d60] -set CM_IDLEST_DPLL_MPU [expr $PRCM_BASE_ADDR + 0x2d64] -set CM_CLKSEL_DPLL_MPU [expr $PRCM_BASE_ADDR + 0x2d6c] -set CM_DIV_M2_DPLL_MPU [expr $PRCM_BASE_ADDR + 0x2d70] -set CM_SSC_DELTAMSTEP_DPLL_MPU [expr $PRCM_BASE_ADDR + 0x2d88] -set CM_SSC_MODFREQDIV_DPLL_MPU [expr $PRCM_BASE_ADDR + 0x2d8c] -set CM_CLKMODE_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2da0] -set CM_IDLEST_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2da4] -set CM_CLKSEL_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2dac] -set CM_DIV_M2_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2db0] -set CM_DIV_M4_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2db8] -set CM_SSC_DELTAMSTEP_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2dc8] -set CM_SSC_MODFREQDIV_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2dcc] -set CM_CLKMODE_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2de0] -set CM_IDLEST_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2de4] -set CM_CLKSEL_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2dec] -set CM_DIV_M2_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2df0] -set CM_CLKSEL2_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2e04] -set CM_SSC_DELTAMSTEP_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2e08] -set CM_SSC_MODFREQDIV_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2e0c] -set CM_CLKDCOLDO_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2e14] -set CM_CLKMODE_DPLL_DISP [expr $PRCM_BASE_ADDR + 0x2e20] -set CM_IDLEST_DPLL_DISP [expr $PRCM_BASE_ADDR + 0x2e24] -set CM_CLKSEL_DPLL_DISP [expr $PRCM_BASE_ADDR + 0x2e2c] -set CM_DIV_M2_DPLL_DISP [expr $PRCM_BASE_ADDR + 0x2e30] -set CM_SSC_DELTAMSTEP_DPLL_DISP [expr $PRCM_BASE_ADDR + 0x2e48] -set CM_SSC_MODFREQDIV_DPLL_DISP [expr $PRCM_BASE_ADDR + 0x2e4c] -set CM_CLKMODE_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e60] -set CM_IDLEST_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e64] -set CM_CLKSEL_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e6c] -set CM_DIV_M2_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e70] -set CM_CLKSEL2_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e84] -set CM_SSC_DELTAMSTEP_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e88] -set CM_SSC_MODFREQDIV_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e8c] -set CM_SHADOW_FREQ_CONFIG1 [expr $PRCM_BASE_ADDR + 0x2fa0] -set CM_SHADOW_FREQ_CONFIG2 [expr $PRCM_BASE_ADDR + 0x2fa4] -set CM_CLKOUT1_CTRL [expr $PRCM_BASE_ADDR + 0x4100] -set CM_DLL_CTRL [expr $PRCM_BASE_ADDR + 0x4104] -set CM_CLKOUT2_CTRL [expr $PRCM_BASE_ADDR + 0x4108] -set CLKSEL_TIMER1MS_CLK [expr $PRCM_BASE_ADDR + 0x4200] -set CLKSEL_TIMER2_CLK [expr $PRCM_BASE_ADDR + 0x4204] -set CLKSEL_TIMER3_CLK [expr $PRCM_BASE_ADDR + 0x4208] -set CLKSEL_TIMER4_CLK [expr $PRCM_BASE_ADDR + 0x420c] -set CLKSEL_TIMER5_CLK [expr $PRCM_BASE_ADDR + 0x4210] -set CLKSEL_TIMER6_CLK [expr $PRCM_BASE_ADDR + 0x4214] -set CLKSEL_TIMER7_CLK [expr $PRCM_BASE_ADDR + 0x4218] -set CLKSEL_TIMER8_CLK [expr $PRCM_BASE_ADDR + 0x421c] -set CLKSEL_TIMER9_CLK [expr $PRCM_BASE_ADDR + 0x4220] -set CLKSEL_TIMER10_CLK [expr $PRCM_BASE_ADDR + 0x4224] -set CLKSEL_TIMER11_CLK [expr $PRCM_BASE_ADDR + 0x4228] -set CLKSEL_WDT1_CLK [expr $PRCM_BASE_ADDR + 0x422c] -set CLKSEL_SYNCTIMER_CLK [expr $PRCM_BASE_ADDR + 0x4230] -set CLKSEL_MAC_CLK [expr $PRCM_BASE_ADDR + 0x4234] -set CLKSEL_CPTS_RFT_CLK [expr $PRCM_BASE_ADDR + 0x4238] -set CLKSEL_GFX_FCLK [expr $PRCM_BASE_ADDR + 0x423c] -set CLKSEL_GPIO0_DBCLK [expr $PRCM_BASE_ADDR + 0x4240] -set CLKSEL_LCDC_PIXEL_CLK [expr $PRCM_BASE_ADDR + 0x4244] -set CLKSEL_ICSS_OCP_CLK [expr $PRCM_BASE_ADDR + 0x4248] -set CLKSEL_DLL_AGING_CLK [expr $PRCM_BASE_ADDR + 0x4250] -set CLKSEL_USBPHY32KHZ_GCLK [expr $PRCM_BASE_ADDR + 0x4260] -set CM_MPU_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8300] -set CM_MPU_MPU_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8320] -set CM_GFX_L3_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8400] -set CM_GFX_GFX_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8420] -set CM_RTC_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8500] -set CM_RTC_RTC_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8520] -set CM_PER_L3_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8800] -set CM_PER_L3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8820] -set CM_PER_AES0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8828] -set CM_PER_DES_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8830] -set CM_PER_CRYPTODMA_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8838] -set CM_PER_L3_INSTR_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8840] -set CM_PER_MSTR_EXPS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8848] -set CM_PER_OCMCRAM_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8850] -set CM_PER_SHA0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8858] -set CM_PER_SLV_EXPS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8860] -set CM_PER_VPFE0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8868] -set CM_PER_VPFE1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8870] -set CM_PER_TPCC_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8878] -set CM_PER_TPTC0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8880] -set CM_PER_TPTC1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8888] -set CM_PER_TPTC2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8890] -set CM_PER_DLL_AGING_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8898] -set CM_PER_L4HS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x88a0] -set CM_PER_L4FW_CLKCTRL [expr $PRCM_BASE_ADDR + 0x88a8] -set CM_PER_L3S_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8a00] -set CM_PER_GPMC_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a20] -set CM_PER_IEEE5000_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a28] -set CM_PER_MCASP0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a38] -set CM_PER_MCASP1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a40] -set CM_PER_MMC2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a48] -set CM_PER_QSPI_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a58] -set CM_PER_USB_OTG_SS0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a60] -set CM_PER_USB_OTG_SS1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a68] -set CM_PER_ICSS_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8b00] -set CM_PER_ICSS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8b20] -set CM_PER_L4LS_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8c00] -set CM_PER_L4LS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c20] -set CM_PER_DCAN0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c28] -set CM_PER_DCAN1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c30] -set CM_PER_EPWMSS0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c38] -set CM_PER_EPWMSS1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c40] -set CM_PER_EPWMSS2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c48] -set CM_PER_EPWMSS3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c50] -set CM_PER_EPWMSS4_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c58] -set CM_PER_EPWMSS5_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c60] -set CM_PER_ELM_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c68] -set CM_PER_GPIO1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c78] -set CM_PER_GPIO2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c80] -set CM_PER_GPIO3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c88] -set CM_PER_GPIO4_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c90] -set CM_PER_GPIO5_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c98] -set CM_PER_HDQ1W_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8ca0] -set CM_PER_I2C1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8ca8] -set CM_PER_I2C2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8cb0] -set CM_PER_MAILBOX0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8cb8] -set CM_PER_MMC0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8cc0] -set CM_PER_MMC1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8cc8] -set CM_PER_PKA_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8cd0] -set CM_PER_RNG_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8ce0] -set CM_PER_SPARE0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8ce8] -set CM_PER_SPARE1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8cf0] -set CM_PER_SPI0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d00] -set CM_PER_SPI1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d08] -set CM_PER_SPI2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d10] -set CM_PER_SPI3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d18] -set CM_PER_SPI4_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d20] -set CM_PER_SPINLOCK_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d28] -set CM_PER_TIMER2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d30] -set CM_PER_TIMER3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d38] -set CM_PER_TIMER4_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d40] -set CM_PER_TIMER5_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d48] -set CM_PER_TIMER6_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d50] -set CM_PER_TIMER7_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d58] -set CM_PER_TIMER8_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d60] -set CM_PER_TIMER9_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d68] -set CM_PER_TIMER10_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d70] -set CM_PER_TIMER11_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d78] -set CM_PER_UART1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d80] -set CM_PER_UART2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d88] -set CM_PER_UART3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d90] -set CM_PER_UART4_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d98] -set CM_PER_UART5_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8da0] -set CM_PER_USBPHYOCP2SCP0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8db8] -set CM_PER_USBPHYOCP2SCP1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8dc0] -set CM_PER_EMIF_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8f00] -set CM_PER_EMIF_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8f20] -set CM_PER_DLL_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8f28] -set CM_PER_EMIF_FW_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8f30] -set CM_PER_OTFA_EMIF_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8f38] -set CM_PER_DSS_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x9200] -set CM_PER_DSS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x9220] -set CM_PER_CPSW_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x9300] -set CM_PER_CPGMAC0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x9320] -set CM_PER_OCPWP_L3_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x9400] -set CM_PER_OCPWP_CLKCTRL [expr $PRCM_BASE_ADDR + 0x9420] +set REVISION_PRM [expr {$PRCM_BASE_ADDR + 0x0000}] +set PRM_IRQSTATUS_MPU [expr {$PRCM_BASE_ADDR + 0x0004}] +set PRM_IRQENABLE_MPU [expr {$PRCM_BASE_ADDR + 0x0008}] +set PRM_IRQSTATUS_M3 [expr {$PRCM_BASE_ADDR + 0x000c}] +set PRM_IRQENABLE_M3 [expr {$PRCM_BASE_ADDR + 0x0010}] +set PM_MPU_PWRSTCTRL [expr {$PRCM_BASE_ADDR + 0x0300}] +set PM_MPU_PWRSTST [expr {$PRCM_BASE_ADDR + 0x0304}] +set RM_MPU_RSTST [expr {$PRCM_BASE_ADDR + 0x0314}] +set RM_MPU_CONTEXT [expr {$PRCM_BASE_ADDR + 0x0324}] +set PM_GFX_PWRSTCTRL [expr {$PRCM_BASE_ADDR + 0x0400}] +set PM_GFX_PWRSTST [expr {$PRCM_BASE_ADDR + 0x0404}] +set RM_GFX_RSTCTRL [expr {$PRCM_BASE_ADDR + 0x0410}] +set RM_GFX_RSTST [expr {$PRCM_BASE_ADDR + 0x0414}] +set RM_GFX_CONTEXT [expr {$PRCM_BASE_ADDR + 0x0424}] +set RM_RTC_CONTEXT [expr {$PRCM_BASE_ADDR + 0x0524}] +set RM_WKUP_RSTCTRL [expr {$PRCM_BASE_ADDR + 0x2010}] +set RM_WKUP_RSTST [expr {$PRCM_BASE_ADDR + 0x2014}] +set CM_L3_AON_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x2800}] +set CM_WKUP_DEBUGSS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2820}] +set CM_L3S_TSC_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x2900}] +set CM_WKUP_ADC_TSC_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2920}] +set CM_L4_WKUP_AON_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x2a00}] +set CM_WKUP_L4WKUP_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2a20}] +set CM_WKUP_WKUP_M3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2a28}] +set CM_WKUP_SYNCTIMER_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2a30}] +set CM_WKUP_CLKDIV32K_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2a38}] +set CM_WKUP_USBPHY0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2a40}] +set CM_WKUP_USBPHY1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2a48}] +set CM_WKUP_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x2b00}] +set CM_WKUP_TIMER0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b20}] +set CM_WKUP_TIMER1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b28}] +set CM_WKUP_WDT0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b30}] +set CM_WKUP_WDT1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b38}] +set CM_WKUP_I2C0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b40}] +set CM_WKUP_UART0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b48}] +set CM_WKUP_SMARTREFLEX0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b50}] +set CM_WKUP_SMARTREFLEX1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b58}] +set CM_WKUP_CONTROL_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b60}] +set CM_WKUP_GPIO0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b68}] +set CM_CLKMODE_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d20}] +set CM_IDLEST_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d24}] +set CM_CLKSEL_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d2c}] +set CM_DIV_M4_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d38}] +set CM_DIV_M5_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d3c}] +set CM_DIV_M6_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d40}] +set CM_SSC_DELTAMSTEP_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d48}] +set CM_SSC_MODFREQDIV_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d4c}] +set CM_CLKMODE_DPLL_MPU [expr {$PRCM_BASE_ADDR + 0x2d60}] +set CM_IDLEST_DPLL_MPU [expr {$PRCM_BASE_ADDR + 0x2d64}] +set CM_CLKSEL_DPLL_MPU [expr {$PRCM_BASE_ADDR + 0x2d6c}] +set CM_DIV_M2_DPLL_MPU [expr {$PRCM_BASE_ADDR + 0x2d70}] +set CM_SSC_DELTAMSTEP_DPLL_MPU [expr {$PRCM_BASE_ADDR + 0x2d88}] +set CM_SSC_MODFREQDIV_DPLL_MPU [expr {$PRCM_BASE_ADDR + 0x2d8c}] +set CM_CLKMODE_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2da0}] +set CM_IDLEST_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2da4}] +set CM_CLKSEL_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2dac}] +set CM_DIV_M2_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2db0}] +set CM_DIV_M4_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2db8}] +set CM_SSC_DELTAMSTEP_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2dc8}] +set CM_SSC_MODFREQDIV_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2dcc}] +set CM_CLKMODE_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2de0}] +set CM_IDLEST_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2de4}] +set CM_CLKSEL_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2dec}] +set CM_DIV_M2_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2df0}] +set CM_CLKSEL2_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2e04}] +set CM_SSC_DELTAMSTEP_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2e08}] +set CM_SSC_MODFREQDIV_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2e0c}] +set CM_CLKDCOLDO_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2e14}] +set CM_CLKMODE_DPLL_DISP [expr {$PRCM_BASE_ADDR + 0x2e20}] +set CM_IDLEST_DPLL_DISP [expr {$PRCM_BASE_ADDR + 0x2e24}] +set CM_CLKSEL_DPLL_DISP [expr {$PRCM_BASE_ADDR + 0x2e2c}] +set CM_DIV_M2_DPLL_DISP [expr {$PRCM_BASE_ADDR + 0x2e30}] +set CM_SSC_DELTAMSTEP_DPLL_DISP [expr {$PRCM_BASE_ADDR + 0x2e48}] +set CM_SSC_MODFREQDIV_DPLL_DISP [expr {$PRCM_BASE_ADDR + 0x2e4c}] +set CM_CLKMODE_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e60}] +set CM_IDLEST_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e64}] +set CM_CLKSEL_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e6c}] +set CM_DIV_M2_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e70}] +set CM_CLKSEL2_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e84}] +set CM_SSC_DELTAMSTEP_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e88}] +set CM_SSC_MODFREQDIV_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e8c}] +set CM_SHADOW_FREQ_CONFIG1 [expr {$PRCM_BASE_ADDR + 0x2fa0}] +set CM_SHADOW_FREQ_CONFIG2 [expr {$PRCM_BASE_ADDR + 0x2fa4}] +set CM_CLKOUT1_CTRL [expr {$PRCM_BASE_ADDR + 0x4100}] +set CM_DLL_CTRL [expr {$PRCM_BASE_ADDR + 0x4104}] +set CM_CLKOUT2_CTRL [expr {$PRCM_BASE_ADDR + 0x4108}] +set CLKSEL_TIMER1MS_CLK [expr {$PRCM_BASE_ADDR + 0x4200}] +set CLKSEL_TIMER2_CLK [expr {$PRCM_BASE_ADDR + 0x4204}] +set CLKSEL_TIMER3_CLK [expr {$PRCM_BASE_ADDR + 0x4208}] +set CLKSEL_TIMER4_CLK [expr {$PRCM_BASE_ADDR + 0x420c}] +set CLKSEL_TIMER5_CLK [expr {$PRCM_BASE_ADDR + 0x4210}] +set CLKSEL_TIMER6_CLK [expr {$PRCM_BASE_ADDR + 0x4214}] +set CLKSEL_TIMER7_CLK [expr {$PRCM_BASE_ADDR + 0x4218}] +set CLKSEL_TIMER8_CLK [expr {$PRCM_BASE_ADDR + 0x421c}] +set CLKSEL_TIMER9_CLK [expr {$PRCM_BASE_ADDR + 0x4220}] +set CLKSEL_TIMER10_CLK [expr {$PRCM_BASE_ADDR + 0x4224}] +set CLKSEL_TIMER11_CLK [expr {$PRCM_BASE_ADDR + 0x4228}] +set CLKSEL_WDT1_CLK [expr {$PRCM_BASE_ADDR + 0x422c}] +set CLKSEL_SYNCTIMER_CLK [expr {$PRCM_BASE_ADDR + 0x4230}] +set CLKSEL_MAC_CLK [expr {$PRCM_BASE_ADDR + 0x4234}] +set CLKSEL_CPTS_RFT_CLK [expr {$PRCM_BASE_ADDR + 0x4238}] +set CLKSEL_GFX_FCLK [expr {$PRCM_BASE_ADDR + 0x423c}] +set CLKSEL_GPIO0_DBCLK [expr {$PRCM_BASE_ADDR + 0x4240}] +set CLKSEL_LCDC_PIXEL_CLK [expr {$PRCM_BASE_ADDR + 0x4244}] +set CLKSEL_ICSS_OCP_CLK [expr {$PRCM_BASE_ADDR + 0x4248}] +set CLKSEL_DLL_AGING_CLK [expr {$PRCM_BASE_ADDR + 0x4250}] +set CLKSEL_USBPHY32KHZ_GCLK [expr {$PRCM_BASE_ADDR + 0x4260}] +set CM_MPU_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8300}] +set CM_MPU_MPU_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8320}] +set CM_GFX_L3_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8400}] +set CM_GFX_GFX_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8420}] +set CM_RTC_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8500}] +set CM_RTC_RTC_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8520}] +set CM_PER_L3_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8800}] +set CM_PER_L3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8820}] +set CM_PER_AES0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8828}] +set CM_PER_DES_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8830}] +set CM_PER_CRYPTODMA_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8838}] +set CM_PER_L3_INSTR_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8840}] +set CM_PER_MSTR_EXPS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8848}] +set CM_PER_OCMCRAM_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8850}] +set CM_PER_SHA0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8858}] +set CM_PER_SLV_EXPS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8860}] +set CM_PER_VPFE0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8868}] +set CM_PER_VPFE1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8870}] +set CM_PER_TPCC_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8878}] +set CM_PER_TPTC0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8880}] +set CM_PER_TPTC1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8888}] +set CM_PER_TPTC2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8890}] +set CM_PER_DLL_AGING_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8898}] +set CM_PER_L4HS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x88a0}] +set CM_PER_L4FW_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x88a8}] +set CM_PER_L3S_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8a00}] +set CM_PER_GPMC_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a20}] +set CM_PER_IEEE5000_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a28}] +set CM_PER_MCASP0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a38}] +set CM_PER_MCASP1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a40}] +set CM_PER_MMC2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a48}] +set CM_PER_QSPI_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a58}] +set CM_PER_USB_OTG_SS0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a60}] +set CM_PER_USB_OTG_SS1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a68}] +set CM_PER_ICSS_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8b00}] +set CM_PER_ICSS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8b20}] +set CM_PER_L4LS_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8c00}] +set CM_PER_L4LS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c20}] +set CM_PER_DCAN0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c28}] +set CM_PER_DCAN1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c30}] +set CM_PER_EPWMSS0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c38}] +set CM_PER_EPWMSS1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c40}] +set CM_PER_EPWMSS2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c48}] +set CM_PER_EPWMSS3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c50}] +set CM_PER_EPWMSS4_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c58}] +set CM_PER_EPWMSS5_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c60}] +set CM_PER_ELM_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c68}] +set CM_PER_GPIO1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c78}] +set CM_PER_GPIO2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c80}] +set CM_PER_GPIO3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c88}] +set CM_PER_GPIO4_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c90}] +set CM_PER_GPIO5_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c98}] +set CM_PER_HDQ1W_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8ca0}] +set CM_PER_I2C1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8ca8}] +set CM_PER_I2C2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8cb0}] +set CM_PER_MAILBOX0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8cb8}] +set CM_PER_MMC0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8cc0}] +set CM_PER_MMC1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8cc8}] +set CM_PER_PKA_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8cd0}] +set CM_PER_RNG_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8ce0}] +set CM_PER_SPARE0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8ce8}] +set CM_PER_SPARE1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8cf0}] +set CM_PER_SPI0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d00}] +set CM_PER_SPI1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d08}] +set CM_PER_SPI2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d10}] +set CM_PER_SPI3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d18}] +set CM_PER_SPI4_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d20}] +set CM_PER_SPINLOCK_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d28}] +set CM_PER_TIMER2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d30}] +set CM_PER_TIMER3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d38}] +set CM_PER_TIMER4_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d40}] +set CM_PER_TIMER5_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d48}] +set CM_PER_TIMER6_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d50}] +set CM_PER_TIMER7_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d58}] +set CM_PER_TIMER8_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d60}] +set CM_PER_TIMER9_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d68}] +set CM_PER_TIMER10_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d70}] +set CM_PER_TIMER11_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d78}] +set CM_PER_UART1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d80}] +set CM_PER_UART2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d88}] +set CM_PER_UART3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d90}] +set CM_PER_UART4_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d98}] +set CM_PER_UART5_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8da0}] +set CM_PER_USBPHYOCP2SCP0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8db8}] +set CM_PER_USBPHYOCP2SCP1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8dc0}] +set CM_PER_EMIF_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8f00}] +set CM_PER_EMIF_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8f20}] +set CM_PER_DLL_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8f28}] +set CM_PER_EMIF_FW_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8f30}] +set CM_PER_OTFA_EMIF_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8f38}] +set CM_PER_DSS_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x9200}] +set CM_PER_DSS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x9220}] +set CM_PER_CPSW_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x9300}] +set CM_PER_CPGMAC0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x9320}] +set CM_PER_OCPWP_L3_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x9400}] +set CM_PER_OCPWP_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x9420}] set CONTROL_BASE_ADDR 0x44e10000 -set CONTROL_STATUS [expr $CONTROL_BASE_ADDR + 0x0040] -set DEVICE_ID [expr $CONTROL_BASE_ADDR + 0x0600] -set DEV_FEATURE [expr $CONTROL_BASE_ADDR + 0x0604] -set DEV_ATTRIBUTE [expr $CONTROL_BASE_ADDR + 0x0610] -set MAC_ID0_LO [expr $CONTROL_BASE_ADDR + 0x0630] -set MAC_ID0_HI [expr $CONTROL_BASE_ADDR + 0x0634] -set MAC_ID1_LO [expr $CONTROL_BASE_ADDR + 0x0638] -set MAC_ID1_HI [expr $CONTROL_BASE_ADDR + 0x063c] -set USB_VID_PID [expr $CONTROL_BASE_ADDR + 0x07f4] -set CONTROL_CONF_ECAP0_IN_PWM0_OUT [expr $CONTROL_BASE_ADDR + 0x0964] -set CONTROL_CONF_SPI4_CS0 [expr $CONTROL_BASE_ADDR + 0x0a5c] -set CONTROL_CONF_SPI2_SCLK [expr $CONTROL_BASE_ADDR + 0x0a60] -set CONTROL_CONF_SPI2_D0 [expr $CONTROL_BASE_ADDR + 0x0a64] -set CONTROL_CONF_XDMA_EVENT_INTR0 [expr $CONTROL_BASE_ADDR + 0x0a70] -set CONTROL_CONF_XDMA_EVENT_INTR1 [expr $CONTROL_BASE_ADDR + 0x0a74] -set CONTROL_CONF_GPMC_A0 [expr $CONTROL_BASE_ADDR + 0x0840] -set DDR_IO_CTRL [expr $CONTROL_BASE_ADDR + 0x0e04] -set VTP_CTRL_REG [expr $CONTROL_BASE_ADDR + 0x0e0c] -set VREF_CTRL [expr $CONTROL_BASE_ADDR + 0x0e14] -set DDR_CKE_CTRL [expr $CONTROL_BASE_ADDR + 0x131c] -set DDR_ADDRCTRL_IOCTRL [expr $CONTROL_BASE_ADDR + 0x1404] -set DDR_ADDRCTRL_WD0_IOCTRL [expr $CONTROL_BASE_ADDR + 0x1408] -set DDR_ADDRCTRL_WD1_IOCTRL [expr $CONTROL_BASE_ADDR + 0x140c] -set DDR_DATA0_IOCTRL [expr $CONTROL_BASE_ADDR + 0x1440] -set DDR_DATA1_IOCTRL [expr $CONTROL_BASE_ADDR + 0x1444] -set DDR_DATA2_IOCTRL [expr $CONTROL_BASE_ADDR + 0x1448] -set DDR_DATA3_IOCTRL [expr $CONTROL_BASE_ADDR + 0x144c] -set EMIF_SDRAM_CONFIG_EXT [expr $CONTROL_BASE_ADDR + 0x1460] -set EMIF_SDRAM_STATUS_EXT [expr $CONTROL_BASE_ADDR + 0x1464] +set CONTROL_STATUS [expr {$CONTROL_BASE_ADDR + 0x0040}] +set DEVICE_ID [expr {$CONTROL_BASE_ADDR + 0x0600}] +set DEV_FEATURE [expr {$CONTROL_BASE_ADDR + 0x0604}] +set DEV_ATTRIBUTE [expr {$CONTROL_BASE_ADDR + 0x0610}] +set MAC_ID0_LO [expr {$CONTROL_BASE_ADDR + 0x0630}] +set MAC_ID0_HI [expr {$CONTROL_BASE_ADDR + 0x0634}] +set MAC_ID1_LO [expr {$CONTROL_BASE_ADDR + 0x0638}] +set MAC_ID1_HI [expr {$CONTROL_BASE_ADDR + 0x063c}] +set USB_VID_PID [expr {$CONTROL_BASE_ADDR + 0x07f4}] +set CONTROL_CONF_ECAP0_IN_PWM0_OUT [expr {$CONTROL_BASE_ADDR + 0x0964}] +set CONTROL_CONF_SPI4_CS0 [expr {$CONTROL_BASE_ADDR + 0x0a5c}] +set CONTROL_CONF_SPI2_SCLK [expr {$CONTROL_BASE_ADDR + 0x0a60}] +set CONTROL_CONF_SPI2_D0 [expr {$CONTROL_BASE_ADDR + 0x0a64}] +set CONTROL_CONF_XDMA_EVENT_INTR0 [expr {$CONTROL_BASE_ADDR + 0x0a70}] +set CONTROL_CONF_XDMA_EVENT_INTR1 [expr {$CONTROL_BASE_ADDR + 0x0a74}] +set CONTROL_CONF_GPMC_A0 [expr {$CONTROL_BASE_ADDR + 0x0840}] +set DDR_IO_CTRL [expr {$CONTROL_BASE_ADDR + 0x0e04}] +set VTP_CTRL_REG [expr {$CONTROL_BASE_ADDR + 0x0e0c}] +set VREF_CTRL [expr {$CONTROL_BASE_ADDR + 0x0e14}] +set DDR_CKE_CTRL [expr {$CONTROL_BASE_ADDR + 0x131c}] +set DDR_ADDRCTRL_IOCTRL [expr {$CONTROL_BASE_ADDR + 0x1404}] +set DDR_ADDRCTRL_WD0_IOCTRL [expr {$CONTROL_BASE_ADDR + 0x1408}] +set DDR_ADDRCTRL_WD1_IOCTRL [expr {$CONTROL_BASE_ADDR + 0x140c}] +set DDR_DATA0_IOCTRL [expr {$CONTROL_BASE_ADDR + 0x1440}] +set DDR_DATA1_IOCTRL [expr {$CONTROL_BASE_ADDR + 0x1444}] +set DDR_DATA2_IOCTRL [expr {$CONTROL_BASE_ADDR + 0x1448}] +set DDR_DATA3_IOCTRL [expr {$CONTROL_BASE_ADDR + 0x144c}] +set EMIF_SDRAM_CONFIG_EXT [expr {$CONTROL_BASE_ADDR + 0x1460}] +set EMIF_SDRAM_STATUS_EXT [expr {$CONTROL_BASE_ADDR + 0x1464}] set GPIO0_BASE_ADDR 0x44e07000 -set GPIO0_SYSCONFIG [expr $GPIO0_BASE_ADDR + 0x0010] -set GPIO0_SYSSTATUS [expr $GPIO0_BASE_ADDR + 0x0114] -set GPIO0_CTRL [expr $GPIO0_BASE_ADDR + 0x0130] -set GPIO0_OE [expr $GPIO0_BASE_ADDR + 0x0134] -set GPIO0_CLEARDATAOUT [expr $GPIO0_BASE_ADDR + 0x0190] -set GPIO0_SETDATAOUT [expr $GPIO0_BASE_ADDR + 0x0194] +set GPIO0_SYSCONFIG [expr {$GPIO0_BASE_ADDR + 0x0010}] +set GPIO0_SYSSTATUS [expr {$GPIO0_BASE_ADDR + 0x0114}] +set GPIO0_CTRL [expr {$GPIO0_BASE_ADDR + 0x0130}] +set GPIO0_OE [expr {$GPIO0_BASE_ADDR + 0x0134}] +set GPIO0_CLEARDATAOUT [expr {$GPIO0_BASE_ADDR + 0x0190}] +set GPIO0_SETDATAOUT [expr {$GPIO0_BASE_ADDR + 0x0194}] set GPIO5_BASE_ADDR 0x48322000 -set GPIO5_SYSCONFIG [expr $GPIO5_BASE_ADDR + 0x0010] -set GPIO5_SYSSTATUS [expr $GPIO5_BASE_ADDR + 0x0114] -set GPIO5_CTRL [expr $GPIO5_BASE_ADDR + 0x0130] -set GPIO5_OE [expr $GPIO5_BASE_ADDR + 0x0134] -set GPIO5_CLEARDATAOUT [expr $GPIO5_BASE_ADDR + 0x0190] -set GPIO5_SETDATAOUT [expr $GPIO5_BASE_ADDR + 0x0194] +set GPIO5_SYSCONFIG [expr {$GPIO5_BASE_ADDR + 0x0010}] +set GPIO5_SYSSTATUS [expr {$GPIO5_BASE_ADDR + 0x0114}] +set GPIO5_CTRL [expr {$GPIO5_BASE_ADDR + 0x0130}] +set GPIO5_OE [expr {$GPIO5_BASE_ADDR + 0x0134}] +set GPIO5_CLEARDATAOUT [expr {$GPIO5_BASE_ADDR + 0x0190}] +set GPIO5_SETDATAOUT [expr {$GPIO5_BASE_ADDR + 0x0194}] set GPIO1_BASE_ADDR 0x4804c000 -set GPIO1_SYSCONFIG [expr $GPIO1_BASE_ADDR + 0x0010] -set GPIO1_SYSSTATUS [expr $GPIO1_BASE_ADDR + 0x0114] -set GPIO1_CTRL [expr $GPIO1_BASE_ADDR + 0x0130] -set GPIO1_OE [expr $GPIO1_BASE_ADDR + 0x0134] -set GPIO1_CLEARDATAOUT [expr $GPIO1_BASE_ADDR + 0x0190] -set GPIO1_SETDATAOUT [expr $GPIO1_BASE_ADDR + 0x0194] +set GPIO1_SYSCONFIG [expr {$GPIO1_BASE_ADDR + 0x0010}] +set GPIO1_SYSSTATUS [expr {$GPIO1_BASE_ADDR + 0x0114}] +set GPIO1_CTRL [expr {$GPIO1_BASE_ADDR + 0x0130}] +set GPIO1_OE [expr {$GPIO1_BASE_ADDR + 0x0134}] +set GPIO1_CLEARDATAOUT [expr {$GPIO1_BASE_ADDR + 0x0190}] +set GPIO1_SETDATAOUT [expr {$GPIO1_BASE_ADDR + 0x0194}] set EMIF_BASE_ADDR 0x4c000000 -set EMIF_STATUS [expr $EMIF_BASE_ADDR + 0x0004] -set EMIF_SDRAM_CONFIG [expr $EMIF_BASE_ADDR + 0x0008] -set EMIF_SDRAM_CONFIG_2 [expr $EMIF_BASE_ADDR + 0x000c] -set EMIF_SDRAM_REF_CTRL [expr $EMIF_BASE_ADDR + 0x0010] -set EMIF_SDRAM_REF_CTRL_SHDW [expr $EMIF_BASE_ADDR + 0x0014] -set EMIF_SDRAM_TIM_1 [expr $EMIF_BASE_ADDR + 0x0018] -set EMIF_SDRAM_TIM_1_SHDW [expr $EMIF_BASE_ADDR + 0x001c] -set EMIF_SDRAM_TIM_2 [expr $EMIF_BASE_ADDR + 0x0020] -set EMIF_SDRAM_TIM_2_SHDW [expr $EMIF_BASE_ADDR + 0x0024] -set EMIF_SDRAM_TIM_3 [expr $EMIF_BASE_ADDR + 0x0028] -set EMIF_SDRAM_TIM_3_SHDW [expr $EMIF_BASE_ADDR + 0x002c] -set EMIF_LPDDR2_NVM_TIM [expr $EMIF_BASE_ADDR + 0x0030] -set EMIF_LPDDR2_NVM_TIM_SHDW [expr $EMIF_BASE_ADDR + 0x0034] -set EMIF_PWR_MGMT_CTRL [expr $EMIF_BASE_ADDR + 0x0038] -set EMIF_PWR_MGMT_CTRL_SHDW [expr $EMIF_BASE_ADDR + 0x003c] -set EMIF_LPDDR2_MODE_REG_DATA [expr $EMIF_BASE_ADDR + 0x0040] -set EMIF_LPDDR2_MODE_REG_CFG [expr $EMIF_BASE_ADDR + 0x0050] -set EMIF_OCP_CONFIG [expr $EMIF_BASE_ADDR + 0x0054] -set EMIF_OCP_CFG_VAL_1 [expr $EMIF_BASE_ADDR + 0x0058] -set EMIF_OCP_CFG_VAL_2 [expr $EMIF_BASE_ADDR + 0x005c] -set EMIF_IODFT_TLGC [expr $EMIF_BASE_ADDR + 0x0060] -set EMIF_IODFT_CTRL_MISR_RSLT [expr $EMIF_BASE_ADDR + 0x0064] -set EMIF_IODFT_ADDR_MISR_RSLT [expr $EMIF_BASE_ADDR + 0x0068] -set EMIF_IODFT_DATA_MISR_RSLT_1 [expr $EMIF_BASE_ADDR + 0x006c] -set EMIF_IODFT_DATA_MISR_RSLT_2 [expr $EMIF_BASE_ADDR + 0x0070] -set EMIF_IODFT_DATA_MISR_RSLT_3 [expr $EMIF_BASE_ADDR + 0x0074] -set EMIF_PERF_CNT_1 [expr $EMIF_BASE_ADDR + 0x0080] -set EMIF_PERF_CNT_2 [expr $EMIF_BASE_ADDR + 0x0084] -set EMIF_PERF_CNT_CFG [expr $EMIF_BASE_ADDR + 0x0088] -set EMIF_PERF_CNT_SEL [expr $EMIF_BASE_ADDR + 0x008c] -set EMIF_PERF_CNT_TIM [expr $EMIF_BASE_ADDR + 0x0090] -set EMIF_MISC_REG [expr $EMIF_BASE_ADDR + 0x0094] -set EMIF_DLL_CALIB_CTRL [expr $EMIF_BASE_ADDR + 0x0098] -set EMIF_DLL_CALIB_CTRL_SHDW [expr $EMIF_BASE_ADDR + 0x009c] -set EMIF_IRQ_EOI [expr $EMIF_BASE_ADDR + 0x00a0] -set EMIF_IRQSTATUS_RAW_SYS [expr $EMIF_BASE_ADDR + 0x00a4] -set EMIF_IRQSTATUS_SYS [expr $EMIF_BASE_ADDR + 0x00ac] -set EMIF_IRQENABLE_SET_SYS [expr $EMIF_BASE_ADDR + 0x00b4] -set EMIF_IRQENABLE_CLR_SYS [expr $EMIF_BASE_ADDR + 0x00bc] -set EMIF_ZQ_CONFIG [expr $EMIF_BASE_ADDR + 0x00c8] -set EMIF_TEMP_ALERT_CONFIG [expr $EMIF_BASE_ADDR + 0x00cc] -set EMIF_OCP_ERR_LOG [expr $EMIF_BASE_ADDR + 0x00d0] -set EMIF_RDWR_LVL_RMP_WIN [expr $EMIF_BASE_ADDR + 0x00d4] -set EMIF_RDWR_LVL_RMP_CTRL [expr $EMIF_BASE_ADDR + 0x00d8] -set EMIF_RDWR_LVL_CTRL [expr $EMIF_BASE_ADDR + 0x00dc] -set EMIF_DDR_PHY_CTRL_1 [expr $EMIF_BASE_ADDR + 0x00e4] -set EMIF_DDR_PHY_CTRL_1_SHDW [expr $EMIF_BASE_ADDR + 0x00e8] -set EMIF_DDR_PHY_CTRL_2 [expr $EMIF_BASE_ADDR + 0x00ec] -set EMIF_PRI_COS_MAP [expr $EMIF_BASE_ADDR + 0x0100] -set EMIF_CONNID_COS_1_MAP [expr $EMIF_BASE_ADDR + 0x0104] -set EMIF_CONNID_COS_2_MAP [expr $EMIF_BASE_ADDR + 0x0108] -set ECC_CTRL [expr $EMIF_BASE_ADDR + 0x0110] -set ECC_ADDR_RNG_1 [expr $EMIF_BASE_ADDR + 0x0114] -set ECC_ADDR_RNG_2 [expr $EMIF_BASE_ADDR + 0x0118] -set EMIF_RD_WR_EXEC_THRSH [expr $EMIF_BASE_ADDR + 0x0120] -set COS_CONFIG [expr $EMIF_BASE_ADDR + 0x0124] - -set PHY_STATUS_1 [expr $EMIF_BASE_ADDR + 0x0144] -set PHY_STATUS_2 [expr $EMIF_BASE_ADDR + 0x0148] -set PHY_STATUS_3 [expr $EMIF_BASE_ADDR + 0x014c] -set PHY_STATUS_4 [expr $EMIF_BASE_ADDR + 0x0150] -set PHY_STATUS_5 [expr $EMIF_BASE_ADDR + 0x0154] -set PHY_STATUS_6 [expr $EMIF_BASE_ADDR + 0x0158] -set PHY_STATUS_7 [expr $EMIF_BASE_ADDR + 0x015c] -set PHY_STATUS_8 [expr $EMIF_BASE_ADDR + 0x0160] -set PHY_STATUS_9 [expr $EMIF_BASE_ADDR + 0x0164] -set PHY_STATUS_10 [expr $EMIF_BASE_ADDR + 0x0168] -set PHY_STATUS_11 [expr $EMIF_BASE_ADDR + 0x016c] -set PHY_STATUS_12 [expr $EMIF_BASE_ADDR + 0x0170] -set PHY_STATUS_13 [expr $EMIF_BASE_ADDR + 0x0174] -set PHY_STATUS_14 [expr $EMIF_BASE_ADDR + 0x0178] -set PHY_STATUS_15 [expr $EMIF_BASE_ADDR + 0x017c] -set PHY_STATUS_16 [expr $EMIF_BASE_ADDR + 0x0180] -set PHY_STATUS_17 [expr $EMIF_BASE_ADDR + 0x0184] -set PHY_STATUS_18 [expr $EMIF_BASE_ADDR + 0x0188] -set PHY_STATUS_19 [expr $EMIF_BASE_ADDR + 0x018c] -set PHY_STATUS_20 [expr $EMIF_BASE_ADDR + 0x0190] -set PHY_STATUS_21 [expr $EMIF_BASE_ADDR + 0x0194] -set PHY_STATUS_22 [expr $EMIF_BASE_ADDR + 0x0198] -set PHY_STATUS_23 [expr $EMIF_BASE_ADDR + 0x019c] -set PHY_STATUS_24 [expr $EMIF_BASE_ADDR + 0x01a0] -set PHY_STATUS_25 [expr $EMIF_BASE_ADDR + 0x01a4] -set PHY_STATUS_26 [expr $EMIF_BASE_ADDR + 0x01a8] -set PHY_STATUS_27 [expr $EMIF_BASE_ADDR + 0x01ac] -set PHY_STATUS_28 [expr $EMIF_BASE_ADDR + 0x01b0] - -set EXT_PHY_CTRL_1 [expr $EMIF_BASE_ADDR + 0x0200] -set EXT_PHY_CTRL_1_SHDW [expr $EMIF_BASE_ADDR + 0x0204] -set EXT_PHY_CTRL_2 [expr $EMIF_BASE_ADDR + 0x0208] -set EXT_PHY_CTRL_2_SHDW [expr $EMIF_BASE_ADDR + 0x020c] -set EXT_PHY_CTRL_3 [expr $EMIF_BASE_ADDR + 0x0210] -set EXT_PHY_CTRL_3_SHDW [expr $EMIF_BASE_ADDR + 0x0214] -set EXT_PHY_CTRL_4 [expr $EMIF_BASE_ADDR + 0x0218] -set EXT_PHY_CTRL_4_SHDW [expr $EMIF_BASE_ADDR + 0x021c] -set EXT_PHY_CTRL_5 [expr $EMIF_BASE_ADDR + 0x0220] -set EXT_PHY_CTRL_5_SHDW [expr $EMIF_BASE_ADDR + 0x0224] -set EXT_PHY_CTRL_6 [expr $EMIF_BASE_ADDR + 0x0228] -set EXT_PHY_CTRL_6_SHDW [expr $EMIF_BASE_ADDR + 0x022c] -set EXT_PHY_CTRL_7 [expr $EMIF_BASE_ADDR + 0x0230] -set EXT_PHY_CTRL_7_SHDW [expr $EMIF_BASE_ADDR + 0x0234] -set EXT_PHY_CTRL_8 [expr $EMIF_BASE_ADDR + 0x0238] -set EXT_PHY_CTRL_8_SHDW [expr $EMIF_BASE_ADDR + 0x023c] -set EXT_PHY_CTRL_9 [expr $EMIF_BASE_ADDR + 0x0240] -set EXT_PHY_CTRL_9_SHDW [expr $EMIF_BASE_ADDR + 0x0244] -set EXT_PHY_CTRL_10 [expr $EMIF_BASE_ADDR + 0x0248] -set EXT_PHY_CTRL_10_SHDW [expr $EMIF_BASE_ADDR + 0x024c] -set EXT_PHY_CTRL_11 [expr $EMIF_BASE_ADDR + 0x0250] -set EXT_PHY_CTRL_11_SHDW [expr $EMIF_BASE_ADDR + 0x0254] -set EXT_PHY_CTRL_12 [expr $EMIF_BASE_ADDR + 0x0258] -set EXT_PHY_CTRL_12_SHDW [expr $EMIF_BASE_ADDR + 0x025c] -set EXT_PHY_CTRL_13 [expr $EMIF_BASE_ADDR + 0x0260] -set EXT_PHY_CTRL_13_SHDW [expr $EMIF_BASE_ADDR + 0x0264] -set EXT_PHY_CTRL_14 [expr $EMIF_BASE_ADDR + 0x0268] -set EXT_PHY_CTRL_14_SHDW [expr $EMIF_BASE_ADDR + 0x026c] -set EXT_PHY_CTRL_15 [expr $EMIF_BASE_ADDR + 0x0270] -set EXT_PHY_CTRL_15_SHDW [expr $EMIF_BASE_ADDR + 0x0274] -set EXT_PHY_CTRL_16 [expr $EMIF_BASE_ADDR + 0x0278] -set EXT_PHY_CTRL_16_SHDW [expr $EMIF_BASE_ADDR + 0x027c] -set EXT_PHY_CTRL_17 [expr $EMIF_BASE_ADDR + 0x0280] -set EXT_PHY_CTRL_17_SHDW [expr $EMIF_BASE_ADDR + 0x0284] -set EXT_PHY_CTRL_18 [expr $EMIF_BASE_ADDR + 0x0288] -set EXT_PHY_CTRL_18_SHDW [expr $EMIF_BASE_ADDR + 0x028c] -set EXT_PHY_CTRL_19 [expr $EMIF_BASE_ADDR + 0x0290] -set EXT_PHY_CTRL_19_SHDW [expr $EMIF_BASE_ADDR + 0x0294] -set EXT_PHY_CTRL_20 [expr $EMIF_BASE_ADDR + 0x0298] -set EXT_PHY_CTRL_20_SHDW [expr $EMIF_BASE_ADDR + 0x029c] -set EXT_PHY_CTRL_21 [expr $EMIF_BASE_ADDR + 0x02a0] -set EXT_PHY_CTRL_21_SHDW [expr $EMIF_BASE_ADDR + 0x02a4] -set EXT_PHY_CTRL_22 [expr $EMIF_BASE_ADDR + 0x02a8] -set EXT_PHY_CTRL_22_SHDW [expr $EMIF_BASE_ADDR + 0x02ac] -set EXT_PHY_CTRL_23 [expr $EMIF_BASE_ADDR + 0x02b0] -set EXT_PHY_CTRL_23_SHDW [expr $EMIF_BASE_ADDR + 0x02b4] -set EXT_PHY_CTRL_24 [expr $EMIF_BASE_ADDR + 0x02b8] -set EXT_PHY_CTRL_24_SHDW [expr $EMIF_BASE_ADDR + 0x02bc] -set EXT_PHY_CTRL_25 [expr $EMIF_BASE_ADDR + 0x02c0] -set EXT_PHY_CTRL_25_SHDW [expr $EMIF_BASE_ADDR + 0x02c4] -set EXT_PHY_CTRL_26 [expr $EMIF_BASE_ADDR + 0x02c8] -set EXT_PHY_CTRL_26_SHDW [expr $EMIF_BASE_ADDR + 0x02cc] -set EXT_PHY_CTRL_27 [expr $EMIF_BASE_ADDR + 0x02d0] -set EXT_PHY_CTRL_27_SHDW [expr $EMIF_BASE_ADDR + 0x02d4] -set EXT_PHY_CTRL_28 [expr $EMIF_BASE_ADDR + 0x02d8] -set EXT_PHY_CTRL_28_SHDW [expr $EMIF_BASE_ADDR + 0x02dc] -set EXT_PHY_CTRL_29 [expr $EMIF_BASE_ADDR + 0x02e0] -set EXT_PHY_CTRL_29_SHDW [expr $EMIF_BASE_ADDR + 0x02e4] -set EXT_PHY_CTRL_30 [expr $EMIF_BASE_ADDR + 0x02e8] -set EXT_PHY_CTRL_30_SHDW [expr $EMIF_BASE_ADDR + 0x02ec] -set EXT_PHY_CTRL_31 [expr $EMIF_BASE_ADDR + 0x02f0] -set EXT_PHY_CTRL_31_SHDW [expr $EMIF_BASE_ADDR + 0x02f4] -set EXT_PHY_CTRL_32 [expr $EMIF_BASE_ADDR + 0x02f8] -set EXT_PHY_CTRL_32_SHDW [expr $EMIF_BASE_ADDR + 0x02fc] -set EXT_PHY_CTRL_33 [expr $EMIF_BASE_ADDR + 0x0300] -set EXT_PHY_CTRL_33_SHDW [expr $EMIF_BASE_ADDR + 0x0304] -set EXT_PHY_CTRL_34 [expr $EMIF_BASE_ADDR + 0x0308] -set EXT_PHY_CTRL_34_SHDW [expr $EMIF_BASE_ADDR + 0x030c] -set EXT_PHY_CTRL_35 [expr $EMIF_BASE_ADDR + 0x0310] -set EXT_PHY_CTRL_35_SHDW [expr $EMIF_BASE_ADDR + 0x0314] -set EXT_PHY_CTRL_36 [expr $EMIF_BASE_ADDR + 0x0318] -set EXT_PHY_CTRL_36_SHDW [expr $EMIF_BASE_ADDR + 0x031c] +set EMIF_STATUS [expr {$EMIF_BASE_ADDR + 0x0004}] +set EMIF_SDRAM_CONFIG [expr {$EMIF_BASE_ADDR + 0x0008}] +set EMIF_SDRAM_CONFIG_2 [expr {$EMIF_BASE_ADDR + 0x000c}] +set EMIF_SDRAM_REF_CTRL [expr {$EMIF_BASE_ADDR + 0x0010}] +set EMIF_SDRAM_REF_CTRL_SHDW [expr {$EMIF_BASE_ADDR + 0x0014}] +set EMIF_SDRAM_TIM_1 [expr {$EMIF_BASE_ADDR + 0x0018}] +set EMIF_SDRAM_TIM_1_SHDW [expr {$EMIF_BASE_ADDR + 0x001c}] +set EMIF_SDRAM_TIM_2 [expr {$EMIF_BASE_ADDR + 0x0020}] +set EMIF_SDRAM_TIM_2_SHDW [expr {$EMIF_BASE_ADDR + 0x0024}] +set EMIF_SDRAM_TIM_3 [expr {$EMIF_BASE_ADDR + 0x0028}] +set EMIF_SDRAM_TIM_3_SHDW [expr {$EMIF_BASE_ADDR + 0x002c}] +set EMIF_LPDDR2_NVM_TIM [expr {$EMIF_BASE_ADDR + 0x0030}] +set EMIF_LPDDR2_NVM_TIM_SHDW [expr {$EMIF_BASE_ADDR + 0x0034}] +set EMIF_PWR_MGMT_CTRL [expr {$EMIF_BASE_ADDR + 0x0038}] +set EMIF_PWR_MGMT_CTRL_SHDW [expr {$EMIF_BASE_ADDR + 0x003c}] +set EMIF_LPDDR2_MODE_REG_DATA [expr {$EMIF_BASE_ADDR + 0x0040}] +set EMIF_LPDDR2_MODE_REG_CFG [expr {$EMIF_BASE_ADDR + 0x0050}] +set EMIF_OCP_CONFIG [expr {$EMIF_BASE_ADDR + 0x0054}] +set EMIF_OCP_CFG_VAL_1 [expr {$EMIF_BASE_ADDR + 0x0058}] +set EMIF_OCP_CFG_VAL_2 [expr {$EMIF_BASE_ADDR + 0x005c}] +set EMIF_IODFT_TLGC [expr {$EMIF_BASE_ADDR + 0x0060}] +set EMIF_IODFT_CTRL_MISR_RSLT [expr {$EMIF_BASE_ADDR + 0x0064}] +set EMIF_IODFT_ADDR_MISR_RSLT [expr {$EMIF_BASE_ADDR + 0x0068}] +set EMIF_IODFT_DATA_MISR_RSLT_1 [expr {$EMIF_BASE_ADDR + 0x006c}] +set EMIF_IODFT_DATA_MISR_RSLT_2 [expr {$EMIF_BASE_ADDR + 0x0070}] +set EMIF_IODFT_DATA_MISR_RSLT_3 [expr {$EMIF_BASE_ADDR + 0x0074}] +set EMIF_PERF_CNT_1 [expr {$EMIF_BASE_ADDR + 0x0080}] +set EMIF_PERF_CNT_2 [expr {$EMIF_BASE_ADDR + 0x0084}] +set EMIF_PERF_CNT_CFG [expr {$EMIF_BASE_ADDR + 0x0088}] +set EMIF_PERF_CNT_SEL [expr {$EMIF_BASE_ADDR + 0x008c}] +set EMIF_PERF_CNT_TIM [expr {$EMIF_BASE_ADDR + 0x0090}] +set EMIF_MISC_REG [expr {$EMIF_BASE_ADDR + 0x0094}] +set EMIF_DLL_CALIB_CTRL [expr {$EMIF_BASE_ADDR + 0x0098}] +set EMIF_DLL_CALIB_CTRL_SHDW [expr {$EMIF_BASE_ADDR + 0x009c}] +set EMIF_IRQ_EOI [expr {$EMIF_BASE_ADDR + 0x00a0}] +set EMIF_IRQSTATUS_RAW_SYS [expr {$EMIF_BASE_ADDR + 0x00a4}] +set EMIF_IRQSTATUS_SYS [expr {$EMIF_BASE_ADDR + 0x00ac}] +set EMIF_IRQENABLE_SET_SYS [expr {$EMIF_BASE_ADDR + 0x00b4}] +set EMIF_IRQENABLE_CLR_SYS [expr {$EMIF_BASE_ADDR + 0x00bc}] +set EMIF_ZQ_CONFIG [expr {$EMIF_BASE_ADDR + 0x00c8}] +set EMIF_TEMP_ALERT_CONFIG [expr {$EMIF_BASE_ADDR + 0x00cc}] +set EMIF_OCP_ERR_LOG [expr {$EMIF_BASE_ADDR + 0x00d0}] +set EMIF_RDWR_LVL_RMP_WIN [expr {$EMIF_BASE_ADDR + 0x00d4}] +set EMIF_RDWR_LVL_RMP_CTRL [expr {$EMIF_BASE_ADDR + 0x00d8}] +set EMIF_RDWR_LVL_CTRL [expr {$EMIF_BASE_ADDR + 0x00dc}] +set EMIF_DDR_PHY_CTRL_1 [expr {$EMIF_BASE_ADDR + 0x00e4}] +set EMIF_DDR_PHY_CTRL_1_SHDW [expr {$EMIF_BASE_ADDR + 0x00e8}] +set EMIF_DDR_PHY_CTRL_2 [expr {$EMIF_BASE_ADDR + 0x00ec}] +set EMIF_PRI_COS_MAP [expr {$EMIF_BASE_ADDR + 0x0100}] +set EMIF_CONNID_COS_1_MAP [expr {$EMIF_BASE_ADDR + 0x0104}] +set EMIF_CONNID_COS_2_MAP [expr {$EMIF_BASE_ADDR + 0x0108}] +set ECC_CTRL [expr {$EMIF_BASE_ADDR + 0x0110}] +set ECC_ADDR_RNG_1 [expr {$EMIF_BASE_ADDR + 0x0114}] +set ECC_ADDR_RNG_2 [expr {$EMIF_BASE_ADDR + 0x0118}] +set EMIF_RD_WR_EXEC_THRSH [expr {$EMIF_BASE_ADDR + 0x0120}] +set COS_CONFIG [expr {$EMIF_BASE_ADDR + 0x0124}] + +set PHY_STATUS_1 [expr {$EMIF_BASE_ADDR + 0x0144}] +set PHY_STATUS_2 [expr {$EMIF_BASE_ADDR + 0x0148}] +set PHY_STATUS_3 [expr {$EMIF_BASE_ADDR + 0x014c}] +set PHY_STATUS_4 [expr {$EMIF_BASE_ADDR + 0x0150}] +set PHY_STATUS_5 [expr {$EMIF_BASE_ADDR + 0x0154}] +set PHY_STATUS_6 [expr {$EMIF_BASE_ADDR + 0x0158}] +set PHY_STATUS_7 [expr {$EMIF_BASE_ADDR + 0x015c}] +set PHY_STATUS_8 [expr {$EMIF_BASE_ADDR + 0x0160}] +set PHY_STATUS_9 [expr {$EMIF_BASE_ADDR + 0x0164}] +set PHY_STATUS_10 [expr {$EMIF_BASE_ADDR + 0x0168}] +set PHY_STATUS_11 [expr {$EMIF_BASE_ADDR + 0x016c}] +set PHY_STATUS_12 [expr {$EMIF_BASE_ADDR + 0x0170}] +set PHY_STATUS_13 [expr {$EMIF_BASE_ADDR + 0x0174}] +set PHY_STATUS_14 [expr {$EMIF_BASE_ADDR + 0x0178}] +set PHY_STATUS_15 [expr {$EMIF_BASE_ADDR + 0x017c}] +set PHY_STATUS_16 [expr {$EMIF_BASE_ADDR + 0x0180}] +set PHY_STATUS_17 [expr {$EMIF_BASE_ADDR + 0x0184}] +set PHY_STATUS_18 [expr {$EMIF_BASE_ADDR + 0x0188}] +set PHY_STATUS_19 [expr {$EMIF_BASE_ADDR + 0x018c}] +set PHY_STATUS_20 [expr {$EMIF_BASE_ADDR + 0x0190}] +set PHY_STATUS_21 [expr {$EMIF_BASE_ADDR + 0x0194}] +set PHY_STATUS_22 [expr {$EMIF_BASE_ADDR + 0x0198}] +set PHY_STATUS_23 [expr {$EMIF_BASE_ADDR + 0x019c}] +set PHY_STATUS_24 [expr {$EMIF_BASE_ADDR + 0x01a0}] +set PHY_STATUS_25 [expr {$EMIF_BASE_ADDR + 0x01a4}] +set PHY_STATUS_26 [expr {$EMIF_BASE_ADDR + 0x01a8}] +set PHY_STATUS_27 [expr {$EMIF_BASE_ADDR + 0x01ac}] +set PHY_STATUS_28 [expr {$EMIF_BASE_ADDR + 0x01b0}] + +set EXT_PHY_CTRL_1 [expr {$EMIF_BASE_ADDR + 0x0200}] +set EXT_PHY_CTRL_1_SHDW [expr {$EMIF_BASE_ADDR + 0x0204}] +set EXT_PHY_CTRL_2 [expr {$EMIF_BASE_ADDR + 0x0208}] +set EXT_PHY_CTRL_2_SHDW [expr {$EMIF_BASE_ADDR + 0x020c}] +set EXT_PHY_CTRL_3 [expr {$EMIF_BASE_ADDR + 0x0210}] +set EXT_PHY_CTRL_3_SHDW [expr {$EMIF_BASE_ADDR + 0x0214}] +set EXT_PHY_CTRL_4 [expr {$EMIF_BASE_ADDR + 0x0218}] +set EXT_PHY_CTRL_4_SHDW [expr {$EMIF_BASE_ADDR + 0x021c}] +set EXT_PHY_CTRL_5 [expr {$EMIF_BASE_ADDR + 0x0220}] +set EXT_PHY_CTRL_5_SHDW [expr {$EMIF_BASE_ADDR + 0x0224}] +set EXT_PHY_CTRL_6 [expr {$EMIF_BASE_ADDR + 0x0228}] +set EXT_PHY_CTRL_6_SHDW [expr {$EMIF_BASE_ADDR + 0x022c}] +set EXT_PHY_CTRL_7 [expr {$EMIF_BASE_ADDR + 0x0230}] +set EXT_PHY_CTRL_7_SHDW [expr {$EMIF_BASE_ADDR + 0x0234}] +set EXT_PHY_CTRL_8 [expr {$EMIF_BASE_ADDR + 0x0238}] +set EXT_PHY_CTRL_8_SHDW [expr {$EMIF_BASE_ADDR + 0x023c}] +set EXT_PHY_CTRL_9 [expr {$EMIF_BASE_ADDR + 0x0240}] +set EXT_PHY_CTRL_9_SHDW [expr {$EMIF_BASE_ADDR + 0x0244}] +set EXT_PHY_CTRL_10 [expr {$EMIF_BASE_ADDR + 0x0248}] +set EXT_PHY_CTRL_10_SHDW [expr {$EMIF_BASE_ADDR + 0x024c}] +set EXT_PHY_CTRL_11 [expr {$EMIF_BASE_ADDR + 0x0250}] +set EXT_PHY_CTRL_11_SHDW [expr {$EMIF_BASE_ADDR + 0x0254}] +set EXT_PHY_CTRL_12 [expr {$EMIF_BASE_ADDR + 0x0258}] +set EXT_PHY_CTRL_12_SHDW [expr {$EMIF_BASE_ADDR + 0x025c}] +set EXT_PHY_CTRL_13 [expr {$EMIF_BASE_ADDR + 0x0260}] +set EXT_PHY_CTRL_13_SHDW [expr {$EMIF_BASE_ADDR + 0x0264}] +set EXT_PHY_CTRL_14 [expr {$EMIF_BASE_ADDR + 0x0268}] +set EXT_PHY_CTRL_14_SHDW [expr {$EMIF_BASE_ADDR + 0x026c}] +set EXT_PHY_CTRL_15 [expr {$EMIF_BASE_ADDR + 0x0270}] +set EXT_PHY_CTRL_15_SHDW [expr {$EMIF_BASE_ADDR + 0x0274}] +set EXT_PHY_CTRL_16 [expr {$EMIF_BASE_ADDR + 0x0278}] +set EXT_PHY_CTRL_16_SHDW [expr {$EMIF_BASE_ADDR + 0x027c}] +set EXT_PHY_CTRL_17 [expr {$EMIF_BASE_ADDR + 0x0280}] +set EXT_PHY_CTRL_17_SHDW [expr {$EMIF_BASE_ADDR + 0x0284}] +set EXT_PHY_CTRL_18 [expr {$EMIF_BASE_ADDR + 0x0288}] +set EXT_PHY_CTRL_18_SHDW [expr {$EMIF_BASE_ADDR + 0x028c}] +set EXT_PHY_CTRL_19 [expr {$EMIF_BASE_ADDR + 0x0290}] +set EXT_PHY_CTRL_19_SHDW [expr {$EMIF_BASE_ADDR + 0x0294}] +set EXT_PHY_CTRL_20 [expr {$EMIF_BASE_ADDR + 0x0298}] +set EXT_PHY_CTRL_20_SHDW [expr {$EMIF_BASE_ADDR + 0x029c}] +set EXT_PHY_CTRL_21 [expr {$EMIF_BASE_ADDR + 0x02a0}] +set EXT_PHY_CTRL_21_SHDW [expr {$EMIF_BASE_ADDR + 0x02a4}] +set EXT_PHY_CTRL_22 [expr {$EMIF_BASE_ADDR + 0x02a8}] +set EXT_PHY_CTRL_22_SHDW [expr {$EMIF_BASE_ADDR + 0x02ac}] +set EXT_PHY_CTRL_23 [expr {$EMIF_BASE_ADDR + 0x02b0}] +set EXT_PHY_CTRL_23_SHDW [expr {$EMIF_BASE_ADDR + 0x02b4}] +set EXT_PHY_CTRL_24 [expr {$EMIF_BASE_ADDR + 0x02b8}] +set EXT_PHY_CTRL_24_SHDW [expr {$EMIF_BASE_ADDR + 0x02bc}] +set EXT_PHY_CTRL_25 [expr {$EMIF_BASE_ADDR + 0x02c0}] +set EXT_PHY_CTRL_25_SHDW [expr {$EMIF_BASE_ADDR + 0x02c4}] +set EXT_PHY_CTRL_26 [expr {$EMIF_BASE_ADDR + 0x02c8}] +set EXT_PHY_CTRL_26_SHDW [expr {$EMIF_BASE_ADDR + 0x02cc}] +set EXT_PHY_CTRL_27 [expr {$EMIF_BASE_ADDR + 0x02d0}] +set EXT_PHY_CTRL_27_SHDW [expr {$EMIF_BASE_ADDR + 0x02d4}] +set EXT_PHY_CTRL_28 [expr {$EMIF_BASE_ADDR + 0x02d8}] +set EXT_PHY_CTRL_28_SHDW [expr {$EMIF_BASE_ADDR + 0x02dc}] +set EXT_PHY_CTRL_29 [expr {$EMIF_BASE_ADDR + 0x02e0}] +set EXT_PHY_CTRL_29_SHDW [expr {$EMIF_BASE_ADDR + 0x02e4}] +set EXT_PHY_CTRL_30 [expr {$EMIF_BASE_ADDR + 0x02e8}] +set EXT_PHY_CTRL_30_SHDW [expr {$EMIF_BASE_ADDR + 0x02ec}] +set EXT_PHY_CTRL_31 [expr {$EMIF_BASE_ADDR + 0x02f0}] +set EXT_PHY_CTRL_31_SHDW [expr {$EMIF_BASE_ADDR + 0x02f4}] +set EXT_PHY_CTRL_32 [expr {$EMIF_BASE_ADDR + 0x02f8}] +set EXT_PHY_CTRL_32_SHDW [expr {$EMIF_BASE_ADDR + 0x02fc}] +set EXT_PHY_CTRL_33 [expr {$EMIF_BASE_ADDR + 0x0300}] +set EXT_PHY_CTRL_33_SHDW [expr {$EMIF_BASE_ADDR + 0x0304}] +set EXT_PHY_CTRL_34 [expr {$EMIF_BASE_ADDR + 0x0308}] +set EXT_PHY_CTRL_34_SHDW [expr {$EMIF_BASE_ADDR + 0x030c}] +set EXT_PHY_CTRL_35 [expr {$EMIF_BASE_ADDR + 0x0310}] +set EXT_PHY_CTRL_35_SHDW [expr {$EMIF_BASE_ADDR + 0x0314}] +set EXT_PHY_CTRL_36 [expr {$EMIF_BASE_ADDR + 0x0318}] +set EXT_PHY_CTRL_36_SHDW [expr {$EMIF_BASE_ADDR + 0x031c}] set WDT1_BASE_ADDR 0x44e35000 -set WDT1_W_PEND_WSPR [expr $WDT1_BASE_ADDR + 0x0034] -set WDT1_WSPR [expr $WDT1_BASE_ADDR + 0x0048] +set WDT1_W_PEND_WSPR [expr {$WDT1_BASE_ADDR + 0x0034}] +set WDT1_WSPR [expr {$WDT1_BASE_ADDR + 0x0048}] set RTC_BASE_ADDR 0x44e3e000 -set RTC_KICK0R [expr $RTC_BASE_ADDR + 0x6c] -set RTC_KICK1R [expr $RTC_BASE_ADDR + 0x70] +set RTC_KICK0R [expr {$RTC_BASE_ADDR + 0x6c}] +set RTC_KICK1R [expr {$RTC_BASE_ADDR + 0x70}] if { [info exists CHIPNAME] } { @@ -512,23 +512,23 @@ proc disable_watchdog { } { # Empty body to make sure this executes as fast as possible. # We don't want any delays here otherwise romcode might start # executing and end up changing state of certain IPs. - while { [expr [mrw $WDT1_W_PEND_WSPR] & 0x10] } { } + while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { } mww phys $WDT1_WSPR $WDT_DISABLE_SEQ2 - while { [expr [mrw $WDT1_W_PEND_WSPR] & 0x10] } { } + while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { } } } proc ceil { x y } { - return [ expr ($x + $y - 1) / $y ] + return [ expr {($x + $y - 1) / $y} ] } proc device_type { } { global CONTROL_STATUS set tmp [ mrw $CONTROL_STATUS ] - set tmp [ expr $tmp & 0x700 ] - set tmp [ expr $tmp >> 8 ] + set tmp [ expr {$tmp & 0x700} ] + set tmp [ expr {$tmp >> 8} ] return $tmp } @@ -542,8 +542,8 @@ proc get_input_clock_frequency { } { } set freq [ mrw $CONTROL_STATUS ] - set freq [ expr $freq & 0x00c00000 ] - set freq [ expr $freq >> 22 ] + set freq [ expr {$freq & 0x00c00000} ] + set freq [ expr {$freq >> 22} ] switch $freq { 0 { @@ -578,12 +578,12 @@ proc mpu_pll_config { CLKIN N M M2 } { mww $CM_CLKMODE_DPLL_MPU 0x4 while { !([ mrw $CM_IDLEST_DPLL_MPU ] & 0x0100) } { } - set clksel [ expr $clksel & (~0x7ffff) ] - set clksel [ expr $clksel | ($M << 0x8) | $N ] + set clksel [ expr {$clksel & (~0x7ffff)} ] + set clksel [ expr {$clksel | ($M << 0x8) | $N} ] mww $CM_CLKSEL_DPLL_MPU $clksel - set div_m2 [ expr $div_m2 & (~0x1f) ] - set div_m2 [ expr $div_m2 | $M2 ] + set div_m2 [ expr {$div_m2 & (~0x1f)} ] + set div_m2 [ expr {$div_m2 | $M2} ] mww $CM_DIV_M2_DPLL_MPU $div_m2 mww $CM_CLKMODE_DPLL_MPU 0x7 @@ -605,8 +605,8 @@ proc core_pll_config { CLKIN N M M4 M5 M6 } { mww $CM_CLKMODE_DPLL_CORE 0x4 while { !([ mrw $CM_IDLEST_DPLL_CORE ] & 0x0100) } { } - set clksel [ expr $clksel & (~0x7ffff) ] - set clksel [ expr $clksel | ($M << 0x8) | $N ] + set clksel [ expr {$clksel & (~0x7ffff)} ] + set clksel [ expr {$clksel | ($M << 0x8) | $N} ] mww $CM_CLKSEL_DPLL_CORE $clksel mww $CM_DIV_M4_DPLL_CORE $M4 mww $CM_DIV_M5_DPLL_CORE $M5 @@ -624,8 +624,8 @@ proc per_pll_config { CLKIN N M M2 } { global CM_DIV_M2_DPLL_PER global CM_IDLEST_DPLL_PER - set x [ expr $M * $CLKIN / 1000000 ] - set y [ expr ($N + 1) * 250 ] + set x [ expr {$M * $CLKIN / 1000000} ] + set y [ expr {($N + 1) * 250} ] set sd [ ceil $x $y ] set clksel [ mrw $CM_CLKSEL_DPLL_PER ] @@ -634,12 +634,12 @@ proc per_pll_config { CLKIN N M M2 } { mww $CM_CLKMODE_DPLL_PER 0x4 while { !([ mrw $CM_IDLEST_DPLL_PER ] & 0x0100) } { } - set clksel [ expr $clksel & (~0xff0fffff) ] - set clksel [ expr $clksel | ($M << 0x8) | $N ] - set clksel [ expr $clksel | ($sd << 24) ] + set clksel [ expr {$clksel & (~0xff0fffff)} ] + set clksel [ expr {$clksel | ($M << 0x8) | $N} ] + set clksel [ expr {$clksel | ($sd << 24)} ] mww $CM_CLKSEL_DPLL_PER $clksel - set div_m2 [ expr 0xffffff80 | $M2 ] + set div_m2 [ expr {0xffffff80 | $M2} ] mww $CM_CLKMODE_DPLL_PER 0x7 while { !([ mrw $CM_IDLEST_DPLL_PER ] & 0x01) } { } @@ -660,11 +660,11 @@ proc ddr_pll_config { CLKIN N M M2 M4 } { mww $CM_CLKMODE_DPLL_DDR 0x4 while { !([ mrw $CM_IDLEST_DPLL_DDR ] & 0x0100) } { } - set clksel [ expr $clksel & (~0x7ffff) ] - set clksel [ expr $clksel | ($M << 8) | $N ] + set clksel [ expr {$clksel & (~0x7ffff)} ] + set clksel [ expr {$clksel | ($M << 8) | $N} ] mww $CM_CLKSEL_DPLL_DDR $clksel - set div_m2 [ expr ($div_m2 & 0xffffffe0) | $M2 ] + set div_m2 [ expr {($div_m2 & 0xffffffe0) | $M2} ] mww $CM_DIV_M2_DPLL_DDR $div_m2 mww $CM_DIV_M4_DPLL_DDR $M4 @@ -725,13 +725,13 @@ proc emif_prcm_clk_enable { } { proc vtp_enable { } { global VTP_CTRL_REG - set vtp [ expr [ mrw $VTP_CTRL_REG ] | 0x40 ] + set vtp [ expr {[ mrw $VTP_CTRL_REG ] | 0x40 }] mww $VTP_CTRL_REG $vtp - set vtp [ expr [ mrw $VTP_CTRL_REG ] & ~0x01 ] + set vtp [ expr {[ mrw $VTP_CTRL_REG ] & ~0x01 }] mww $VTP_CTRL_REG $vtp - set vtp [ expr [ mrw $VTP_CTRL_REG ] | 0x01 ] + set vtp [ expr {[ mrw $VTP_CTRL_REG ] | 0x01 }] mww $VTP_CTRL_REG $vtp } @@ -849,18 +849,18 @@ proc config_ddr_phy { } { set gatelvl_num_dq0 0x0f set wrlvl_num_dq0 0x0f - mww $EXT_PHY_CTRL_1 [ expr ($slave_ratio << 20) | ($slave_ratio << 10) | $slave_ratio ] - mww $EXT_PHY_CTRL_1_SHDW [ expr ($slave_ratio << 20) | ($slave_ratio << 10) | $slave_ratio ] - mww $EXT_PHY_CTRL_26 [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] - mww $EXT_PHY_CTRL_26_SHDW [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] - mww $EXT_PHY_CTRL_27 [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] - mww $EXT_PHY_CTRL_27_SHDW [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] - mww $EXT_PHY_CTRL_28 [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] - mww $EXT_PHY_CTRL_28_SHDW [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] - mww $EXT_PHY_CTRL_29 [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] - mww $EXT_PHY_CTRL_29_SHDW [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] - mww $EXT_PHY_CTRL_30 [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] - mww $EXT_PHY_CTRL_30_SHDW [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] + mww $EXT_PHY_CTRL_1 [ expr {($slave_ratio << 20) | ($slave_ratio << 10) | $slave_ratio} ] + mww $EXT_PHY_CTRL_1_SHDW [ expr {($slave_ratio << 20) | ($slave_ratio << 10) | $slave_ratio} ] + mww $EXT_PHY_CTRL_26 [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] + mww $EXT_PHY_CTRL_26_SHDW [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] + mww $EXT_PHY_CTRL_27 [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] + mww $EXT_PHY_CTRL_27_SHDW [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] + mww $EXT_PHY_CTRL_28 [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] + mww $EXT_PHY_CTRL_28_SHDW [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] + mww $EXT_PHY_CTRL_29 [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] + mww $EXT_PHY_CTRL_29_SHDW [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] + mww $EXT_PHY_CTRL_30 [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] + mww $EXT_PHY_CTRL_30_SHDW [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] mww $EXT_PHY_CTRL_31 0x00 mww $EXT_PHY_CTRL_31_SHDW 0x00 mww $EXT_PHY_CTRL_32 0x00 @@ -873,14 +873,14 @@ proc config_ddr_phy { } { mww $EXT_PHY_CTRL_35_SHDW 0x00 mww $EXT_PHY_CTRL_22 0x00 mww $EXT_PHY_CTRL_22_SHDW 0x00 - mww $EXT_PHY_CTRL_23 [ expr ($wr_dqs_slave_delay << 16) | $rd_dqs_slave_delay ] - mww $EXT_PHY_CTRL_23_SHDW [ expr ($wr_dqs_slave_delay << 16) | $rd_dqs_slave_delay ] - mww $EXT_PHY_CTRL_24 [ expr ($dq_offset << 24) | ($gatelvl_init_mode << 16) | $wr_data_slave_delay ] - mww $EXT_PHY_CTRL_24_SHDW [ expr ($dq_offset << 24) | ($gatelvl_init_mode << 16) | $wr_data_slave_delay << 0 ] - mww $EXT_PHY_CTRL_25 [ expr ($dq_offset << 21) | ($dq_offset << 14) | ($dq_offset << 7) | $dq_offset ] - mww $EXT_PHY_CTRL_25_SHDW [ expr ($dq_offset << 21) | ($dq_offset << 14) | ($dq_offset << 7) | $dq_offset ] - mww $EXT_PHY_CTRL_36 [ expr ($wrlvl_num_dq0 << 4) | $gatelvl_num_dq0 ] - mww $EXT_PHY_CTRL_36_SHDW [ expr ($wrlvl_num_dq0 << 4) | $gatelvl_num_dq0 ] + mww $EXT_PHY_CTRL_23 [ expr {($wr_dqs_slave_delay << 16) | $rd_dqs_slave_delay} ] + mww $EXT_PHY_CTRL_23_SHDW [ expr {($wr_dqs_slave_delay << 16) | $rd_dqs_slave_delay} ] + mww $EXT_PHY_CTRL_24 [ expr {($dq_offset << 24) | ($gatelvl_init_mode << 16) | $wr_data_slave_delay} ] + mww $EXT_PHY_CTRL_24_SHDW [ expr {($dq_offset << 24) | ($gatelvl_init_mode << 16) | $wr_data_slave_delay << 0} ] + mww $EXT_PHY_CTRL_25 [ expr {($dq_offset << 21) | ($dq_offset << 14) | ($dq_offset << 7) | $dq_offset} ] + mww $EXT_PHY_CTRL_25_SHDW [ expr {($dq_offset << 21) | ($dq_offset << 14) | ($dq_offset << 7) | $dq_offset} ] + mww $EXT_PHY_CTRL_36 [ expr {($wrlvl_num_dq0 << 4) | $gatelvl_num_dq0} ] + mww $EXT_PHY_CTRL_36_SHDW [ expr {($wrlvl_num_dq0 << 4) | $gatelvl_num_dq0} ] } proc config_ddr_timing { } { @@ -948,7 +948,7 @@ proc config_ddr3 { SDRAM_CONFIG } { emif_prcm_clk_enable vtp_enable - set dll [ expr [ mrw $CM_DLL_CTRL ] & ~0x01 ] + set dll [ expr {[ mrw $CM_DLL_CTRL ] & ~0x01 }] mww $CM_DLL_CTRL $dll while { !([ mrw $CM_DLL_CTRL ] & 0x04) } { } @@ -978,7 +978,7 @@ proc config_ddr3 { SDRAM_CONFIG } { sleep 10 - set tmp [ expr [ mrw $EXT_PHY_CTRL_36 ] | 0x0100 ] + set tmp [ expr {[ mrw $EXT_PHY_CTRL_36 ] | 0x0100 }] mww $EXT_PHY_CTRL_36 $tmp mww $EXT_PHY_CTRL_36_SHDW $tmp diff --git a/tcl/target/ampere_emag.cfg b/tcl/target/ampere_emag.cfg index 7115a83..2e828de 100644 --- a/tcl/target/ampere_emag.cfg +++ b/tcl/target/ampere_emag.cfg @@ -78,7 +78,7 @@ for {set _i 0} {$_i < $_NUMCORES} {incr _i} { # Create and configure Cross Trigger Interface (CTI) - required for halt and resume set _CTINAME $_TARGETNAME.cti - cti create $_CTINAME -dap $_DAPNAME -ap-num $_APNUM -baseaddr [expr 0xFC020000 + ($_i << 20)] + cti create $_CTINAME -dap $_DAPNAME -ap-num $_APNUM -baseaddr [expr {0xFC020000 + ($_i << 20)}] # Create the target target create $_TARGETNAME aarch64 -endian $_ENDIAN -dap $_DAPNAME -ap-num $_APNUM -cti $_CTINAME -coreid $_i diff --git a/tcl/target/bluenrg-x.cfg b/tcl/target/bluenrg-x.cfg index a9d321e..ea94be9 100644 --- a/tcl/target/bluenrg-x.cfg +++ b/tcl/target/bluenrg-x.cfg @@ -54,9 +54,9 @@ $_TARGETNAME configure -event halted { if {$_JTAG_IDCODE != 0x0201E041} { # Stop watchdog during halt, if enabled. Only Bluenrg-1/2 set WDOG_VALUE [mrw 0x40700008] - if [expr ($WDOG_VALUE & (1 << 1))] { + if [expr {$WDOG_VALUE & (1 << 1)}] { set WDOG_VALUE_SET 1 - mww 0x40700008 [expr ($WDOG_VALUE & 0xFFFFFFFD)] + mww 0x40700008 [expr {$WDOG_VALUE & 0xFFFFFFFD}] } } } @@ -65,7 +65,7 @@ $_TARGETNAME configure -event resumed { global WDOG_VALUE_SET set _JTAG_IDCODE [mrw 0x40000004] if {$_JTAG_IDCODE != 0x0201E041} { - if [expr $WDOG_VALUE_SET] { + if {$WDOG_VALUE_SET} { # Restore watchdog enable value after resume. Only Bluenrg-1/2 mww 0x40700008 $WDOG_VALUE set WDOG_VALUE_SET 0 diff --git a/tcl/target/c100config.tcl b/tcl/target/c100config.tcl index 53b2c5d..e937219 100644 --- a/tcl/target/c100config.tcl +++ b/tcl/target/c100config.tcl @@ -26,14 +26,14 @@ proc configC100 {} { dict set configC100 w_amba 1 dict set configC100 x_amba 1 # y = amba_clk * (w+1)*(x+1)*2/xtal_clk - dict set configC100 y_amba [expr ([dict get $configC100 CONFIG_SYS_HZ_CLOCK] * ( ([dict get $configC100 w_amba]+1 ) * ([dict get $configC100 x_amba]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]) ] + dict set configC100 y_amba [expr {[dict get $configC100 CONFIG_SYS_HZ_CLOCK] * ( ([dict get $configC100 w_amba]+1 ) * ([dict get $configC100 x_amba]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]} ] # Arm Clk 450MHz, must be a multiple of 25 MHz dict set configC100 CFG_ARM_CLOCK 450000000 dict set configC100 w_arm 0 dict set configC100 x_arm 1 # y = arm_clk * (w+1)*(x+1)*2/xtal_clk - dict set configC100 y_arm [expr ([dict get $configC100 CFG_ARM_CLOCK] * ( ([dict get $configC100 w_arm]+1 ) * ([dict get $configC100 x_arm]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]) ] + dict set configC100 y_arm [expr {[dict get $configC100 CFG_ARM_CLOCK] * ( ([dict get $configC100 w_arm]+1 ) * ([dict get $configC100 x_arm]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]} ] } @@ -43,7 +43,7 @@ proc setupTelo {} { # setup GPIO used as control signals for C100 setupGPIO - # This will allow acces to lower 8MB or NOR + # This will allow access to lower 8MB or NOR lowGPIO5 # setup NOR size,timing,etc. setupNOR @@ -79,7 +79,7 @@ proc setupNOR {} { #mww $EX_CS0_TMG3_REG # set EBUS clock 165/5=33MHz mww $EX_CLOCK_DIV_REG 0x5 - # everthing else is OK with default + # everything else is OK with default } proc bootNOR {} { @@ -111,23 +111,23 @@ proc setupGPIO {} { set GPIO_OE_REG [regs GPIO_OE_REG] # set GPIO29=GPIO17=1, GPIO5=0 - mww $GPIO_OUTPUT_REG [expr 1<<29 | 1<<17] + mww $GPIO_OUTPUT_REG [expr {1<<29 | 1<<17}] # enable [as output] GPIO29,GPIO17,GPIO5 - mww $GPIO_OE_REG [expr 1<<29 | 1<<17 | 1<<5] + mww $GPIO_OE_REG [expr {1<<29 | 1<<17 | 1<<5}] } proc highGPIO5 {} { echo "GPIO5 high" set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG] # set GPIO5=1 - mmw $GPIO_OUTPUT_REG [expr 1 << 5] 0x0 + mmw $GPIO_OUTPUT_REG [expr {1 << 5}] 0x0 } proc lowGPIO5 {} { echo "GPIO5 low" set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG] # set GPIO5=0 - mmw $GPIO_OUTPUT_REG 0x0 [expr 1 << 5] + mmw $GPIO_OUTPUT_REG 0x0 [expr {1 << 5}] } proc boardID {id} { @@ -159,11 +159,11 @@ proc boardID {id} { proc ooma_board_detect {} { set GPIO_BOOTSTRAP_REG [regs GPIO_BOOTSTRAP_REG] - # read the current value of the BOOTSRAP pins + # read the current value of the BOOTSTRAP pins set tmp [mrw $GPIO_BOOTSTRAP_REG] echo [format "GPIO_BOOTSTRAP_REG (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG $tmp] # extract the GPBP bits - set gpbt [expr ($tmp &0x1C00) >> 10 | ($tmp & 0x40) >>3] + set gpbt [expr {($tmp &0x1C00) >> 10 | ($tmp & 0x40) >>3}] # display board ID echo [format "This is %s (0x%x)" [dict get [boardID $gpbt] $gpbt name] $gpbt] @@ -226,13 +226,13 @@ proc configureDDR2regs_256M {} { set wr_dqs_shift 0x40 # start DDRC - mw64bit $DENALI_CTL_02_DATA [expr $DENALI_CTL_02_VAL | (1 << 32)] + mw64bit $DENALI_CTL_02_DATA [expr {$DENALI_CTL_02_VAL | (1 << 32)}] # wait int_status[2] (DRAM init complete) echo -n "Waiting for DDR2 controller to init..." - set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]] - while { [expr $tmp & 0x040000] == 0 } { + set tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]] + while { [expr {$tmp & 0x040000}] == 0 } { sleep 1 - set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]] + set tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]] } echo "done." @@ -294,16 +294,16 @@ proc configureDDR2regs_128M {} { set wr_dqs_shift 0x40 # start DDRC - mw64bit $DENALI_CTL_02_DATA [expr $DENALI_CTL_02_VAL | (1 << 32)] + mw64bit $DENALI_CTL_02_DATA [expr {$DENALI_CTL_02_VAL | (1 << 32)}] # wait int_status[2] (DRAM init complete) echo -n "Waiting for DDR2 controller to init..." - set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]] - while { [expr $tmp & 0x040000] == 0 } { + set tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]] + while { [expr {$tmp & 0x040000}] == 0 } { sleep 1 - set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]] + set tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]] } # This is not necessary - #mw64bit $DENALI_CTL_11_DATA [expr ($DENALI_CTL_11_VAL & ~0x00007F0000000000) | ($wr_dqs_shift << 40) ] + #mw64bit $DENALI_CTL_11_DATA [expr {($DENALI_CTL_11_VAL & ~0x00007F0000000000) | ($wr_dqs_shift << 40)} ] echo "done." # do ddr2 training sequence @@ -341,14 +341,14 @@ proc setupUART0 {} { # Enable Divisor Latch access mmw $UART0_LCR $LCR_DLAB 0x0 # set the divisor to $tmp - mww $UART0_DLL [expr $tmp & 0xff] - mww $UART0_DLH [expr $tmp >> 8] + mww $UART0_DLL [expr {$tmp & 0xff}] + mww $UART0_DLH [expr {$tmp >> 8}] # Disable Divisor Latch access mmw $UART0_LCR 0x0 $LCR_DLAB # set the UART to 8N1 - mmw $UART0_LCR [expr $LCR_ONE_STOP | $LCR_CHAR_LEN_8 ] 0x0 + mmw $UART0_LCR [expr {$LCR_ONE_STOP | $LCR_CHAR_LEN_8} ] 0x0 # reset FIFO - mmw $UART0_IIR [expr $FCR_XMITRES | $FCR_RCVRRES | $FCR_FIFOEN ] 0x0 + mmw $UART0_IIR [expr {$FCR_XMITRES | $FCR_RCVRRES | $FCR_FIFOEN} ] 0x0 # enable FFUART mww $UART0_IER $IER_UUE } @@ -362,7 +362,7 @@ proc putcUART0 {char} { # convert the 'char' to digit set tmp [ scan $char %c ] # /* wait for room in the tx FIFO on FFUART */ - while {[expr [mrw $UART0_LSR] & $LSR_TEMT] == 0} { sleep 1 } + while {[expr {[mrw $UART0_LSR] & $LSR_TEMT}] == 0} { sleep 1 } mww $UART0_THR $tmp if { $char == "\n" } { putcUART0 \r } } @@ -372,7 +372,7 @@ proc putsUART0 {str} { set len [string length $str] while { $index < $len } { putcUART0 [string index $str $index] - set index [expr $index + 1] + set index [expr {$index + 1}] } } diff --git a/tcl/target/c100helper.tcl b/tcl/target/c100helper.tcl index 725ba70..bdcfd8c 100644 --- a/tcl/target/c100helper.tcl +++ b/tcl/target/c100helper.tcl @@ -13,16 +13,16 @@ proc helpC100 {} { echo "10) showArmClk: will show current config registers for Arm Bus Clock" echo "11) setupArmClk: will setup Amba Bus Clock=450MHz" echo "12) ooma_board_detect: will show which version of Telo you have" - echo "13) setupDDR2: will configure DDR2 controller, you must have PLLs configureg" + echo "13) setupDDR2: will configure DDR2 controller, you must have PLLs configured" echo "14) showDDR2: will show DDR2 config registers" echo "15) showWatchdog: will show current register config for watchdog" echo "16) reboot: will trigger watchdog and reboot Telo (hw reset)" echo "17) bootNOR: will boot Telo from NOR" - echo "18) setupUART0: will configure UART0 for 115200 8N1, PLLs have to be confiured" + echo "18) setupUART0: will configure UART0 for 115200 8N1, PLLs have to be configured" echo "19) putcUART0: will print a character on UART0" echo "20) putsUART0: will print a string on UART0" - echo "21) trainDDR2: will run DDR2 training program" - echo "22) flashUBOOT: will prgram NOR sectors 0-3 with u-boot.bin" + echo "21) trainDDR2: will run DDR2 training program" + echo "22) flashUBOOT: will program NOR sectors 0-3 with u-boot.bin" } source [find mem_helper.tcl] @@ -37,11 +37,11 @@ proc mr64bit {reg} { # write a 64-bit register (memory mapped) proc mw64bit {reg value} { - set high [expr $value >> 32] - set low [expr $value & 0xffffffff] + set high [expr {$value >> 32}] + set low [expr {$value & 0xffffffff}] #echo [format "mw64bit(0x%x): 0x%08x%08x" $reg $high $low] mww $reg $low - mww [expr $reg+4] $high + mww [expr {$reg+4}] $high } @@ -119,19 +119,19 @@ proc showAmbaClk {} { echo [format "CLKCORE_AHB_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_AHB_CLK_CNTRL [mrw $CLKCORE_AHB_CLK_CNTRL]] mem2array value 32 $CLKCORE_AHB_CLK_CNTRL 1 # see if the PLL is in bypass mode - set bypass [expr ($value(0) & $PLL_CLK_BYPASS) >> 24 ] + set bypass [expr {($value(0) & $PLL_CLK_BYPASS) >> 24}] echo [format "PLL bypass bit: %d" $bypass] if {$bypass == 1} { - echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr $CFG_REFCLKFREQ/1000000]] + echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr {$CFG_REFCLKFREQ/1000000}]] } else { # nope, extract x,y,w and compute the PLL output freq. - set x [expr ($value(0) & 0x0001F0000) >> 16] + set x [expr {($value(0) & 0x0001F0000) >> 16}] echo [format "x: %d" $x] - set y [expr ($value(0) & 0x00000007F)] + set y [expr {($value(0) & 0x00000007F)}] echo [format "y: %d" $y] - set w [expr ($value(0) & 0x000000300) >> 8] + set w [expr {($value(0) & 0x000000300) >> 8}] echo [format "w: %d" $w] - echo [format "Amba PLL Clk: %d (MHz)" [expr ($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000]] + echo [format "Amba PLL Clk: %d (MHz)" [expr {($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000}]] } } @@ -154,7 +154,7 @@ proc setupAmbaClk {} { set x [config x_amba] set y [config y_amba] - echo [format "Setting Amba PLL to lock to %d MHz" [expr $CONFIG_SYS_HZ_CLOCK/1000000]] + echo [format "Setting Amba PLL to lock to %d MHz" [expr {$CONFIG_SYS_HZ_CLOCK/1000000}]] #echo [format "setupAmbaClk: w= %d" $w] #echo [format "setupAmbaClk: x= %d" $x] #echo [format "setupAmbaClk: y= %d" $y] @@ -174,10 +174,10 @@ proc setupAmbaClk {} { sleep 1 # set X, W and X mmw $CLKCORE_AHB_CLK_CNTRL 0x0 0xFFFFFF - mmw $CLKCORE_AHB_CLK_CNTRL [expr (($x << 16) + ($w << 8) + $y)] 0x0 + mmw $CLKCORE_AHB_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0 # wait for PLL to lock echo "Waiting for Amba PLL to lock" - while {[expr [mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK] == 0} { sleep 1 } + while {[expr {[mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK]} == 0} { sleep 1 } # remove the internal PLL bypass mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $AHB_PLL_BY_CTRL # remove PLL from BYPASS mode using MUX @@ -194,19 +194,19 @@ proc showArmClk {} { echo [format "CLKCORE_ARM_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_ARM_CLK_CNTRL [mrw $CLKCORE_ARM_CLK_CNTRL]] mem2array value 32 $CLKCORE_ARM_CLK_CNTRL 1 # see if the PLL is in bypass mode - set bypass [expr ($value(0) & $PLL_CLK_BYPASS) >> 24 ] + set bypass [expr {($value(0) & $PLL_CLK_BYPASS) >> 24}] echo [format "PLL bypass bit: %d" $bypass] if {$bypass == 1} { - echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr $CFG_REFCLKFREQ/1000000]] + echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr {$CFG_REFCLKFREQ/1000000}]] } else { # nope, extract x,y,w and compute the PLL output freq. - set x [expr ($value(0) & 0x0001F0000) >> 16] + set x [expr {($value(0) & 0x0001F0000) >> 16}] echo [format "x: %d" $x] - set y [expr ($value(0) & 0x00000007F)] + set y [expr {($value(0) & 0x00000007F)}] echo [format "y: %d" $y] - set w [expr ($value(0) & 0x000000300) >> 8] + set w [expr {($value(0) & 0x000000300) >> 8}] echo [format "w: %d" $w] - echo [format "Arm PLL Clk: %d (MHz)" [expr ($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000]] + echo [format "Arm PLL Clk: %d (MHz)" [expr {($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000}]] } } @@ -228,7 +228,7 @@ proc setupArmClk {} { set x [config x_arm] set y [config y_arm] - echo [format "Setting Arm PLL to lock to %d MHz" [expr $CFG_ARM_CLOCK/1000000]] + echo [format "Setting Arm PLL to lock to %d MHz" [expr {$CFG_ARM_CLOCK/1000000}]] #echo [format "setupArmClk: w= %d" $w] #echo [format "setupArmaClk: x= %d" $x] #echo [format "setupArmaClk: y= %d" $y] @@ -248,10 +248,10 @@ proc setupArmClk {} { sleep 1 # set X, W and X mmw $CLKCORE_ARM_CLK_CNTRL 0x0 0xFFFFFF - mmw $CLKCORE_ARM_CLK_CNTRL [expr (($x << 16) + ($w << 8) + $y)] 0x0 + mmw $CLKCORE_ARM_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0 # wait for PLL to lock echo "Waiting for Amba PLL to lock" - while {[expr [mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK] == 0} { sleep 1 } + while {[expr {[mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK]} == 0} { sleep 1 } # remove the internal PLL bypass mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $ARM_PLL_BY_CTRL # remove PLL from BYPASS mode using MUX @@ -281,11 +281,11 @@ proc setupDDR2 {} { # and not reset. mmw $BLOCK_RESET_REG 0x0 $DDR_RST - set M [expr 1024 * 1024] - set DDR_SZ_1024M [expr 1024 * $M] - set DDR_SZ_256M [expr 256 * $M] - set DDR_SZ_128M [expr 128 * $M] - set DDR_SZ_64M [expr 64 * $M] + set M [expr {1024 * 1024}] + set DDR_SZ_1024M [expr {1024 * $M}] + set DDR_SZ_256M [expr {256 * $M}] + set DDR_SZ_128M [expr {128 * $M}] + set DDR_SZ_64M [expr {64 * $M}] # ooma_board_detect returns DDR2 memory size set tmp [ooma_board_detect] if {$tmp == "128M"} { @@ -299,7 +299,7 @@ proc setupDDR2 {} { } # Memory setup register - mww $MEMORY_MAX_ADDR [expr ($ddr_size - 1) + $MEMORY_BASE_ADDR] + mww $MEMORY_MAX_ADDR [expr {($ddr_size - 1) + $MEMORY_BASE_ADDR}] # disable ROM remap mww $MEMORY_CR 0x0 # Take DDR controller out of reset @@ -442,12 +442,12 @@ proc initC100 {} { # APB init # // Setting APB Bus Wait states to 1, set post write # (*(volatile u32*)(APB_ACCESS_WS_REG)) = 0x40; - mww [expr $APB_ACCESS_WS_REG] 0x40 + mww $APB_ACCESS_WS_REG 0x40 # AHB init # // enable all 6 masters for ARAM - mmw $ASA_ARAM_TC_CR_REG [expr $ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN] 0x0 + mmw $ASA_ARAM_TC_CR_REG [expr {$ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN}] 0x0 # // enable all 6 masters for EBUS - mmw $ASA_EBUS_TC_CR_REG [expr $ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN] 0x0 + mmw $ASA_EBUS_TC_CR_REG [expr {$ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN}] 0x0 # ARAM init # // disable pipeline mode in ARAM diff --git a/tcl/target/c100regs.tcl b/tcl/target/c100regs.tcl index a2c7a60..9304808 100644 --- a/tcl/target/c100regs.tcl +++ b/tcl/target/c100regs.tcl @@ -35,43 +35,43 @@ dict set regsC100 EXP_CS4_BASEADDR 0x30000000 dict set regsC100 DDR_BASEADDR 0x80000000 -dict set regsC100 TDM_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x000000] -dict set regsC100 PHI_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x010000] -dict set regsC100 TDMA_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x020000] -dict set regsC100 ASA_DDR_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x040000] -dict set regsC100 ASA_ARAM_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x048000] -dict set regsC100 TIMER_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x050000] -dict set regsC100 ASD_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x060000] -dict set regsC100 GPIO_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x070000] -dict set regsC100 UART0_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x090000] -dict set regsC100 UART1_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x094000] -dict set regsC100 SPI_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x098000] -dict set regsC100 I2C_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x09C000] -dict set regsC100 INTC_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0A0000] -dict set regsC100 CLKCORE_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0B0000] -dict set regsC100 PUI_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0B0000] -dict set regsC100 GEMAC_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0D0000] -dict set regsC100 IDMA_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0E0000] -dict set regsC100 MEMCORE_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0F0000] -dict set regsC100 ASA_EBUS_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x100000] -dict set regsC100 ASA_AAB_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x108000] -dict set regsC100 GEMAC1_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x190000] -dict set regsC100 EBUS_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x1A0000] -dict set regsC100 MDMA_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x1E0000] +dict set regsC100 TDM_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x000000}] +dict set regsC100 PHI_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x010000}] +dict set regsC100 TDMA_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x020000}] +dict set regsC100 ASA_DDR_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x040000}] +dict set regsC100 ASA_ARAM_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x048000}] +dict set regsC100 TIMER_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x050000}] +dict set regsC100 ASD_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x060000}] +dict set regsC100 GPIO_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x070000}] +dict set regsC100 UART0_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x090000}] +dict set regsC100 UART1_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x094000}] +dict set regsC100 SPI_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x098000}] +dict set regsC100 I2C_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x09C000}] +dict set regsC100 INTC_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x0A0000}] +dict set regsC100 CLKCORE_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x0B0000}] +dict set regsC100 PUI_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x0B0000}] +dict set regsC100 GEMAC_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x0D0000}] +dict set regsC100 IDMA_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x0E0000}] +dict set regsC100 MEMCORE_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x0F0000}] +dict set regsC100 ASA_EBUS_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x100000}] +dict set regsC100 ASA_AAB_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x108000}] +dict set regsC100 GEMAC1_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x190000}] +dict set regsC100 EBUS_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x1A0000}] +dict set regsC100 MDMA_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x1E0000}] #//////////////////////////////////////////////////////////// #// AHB block // #//////////////////////////////////////////////////////////// -dict set regsC100 ASA_ARAM_PRI_REG [expr [dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x00] -dict set regsC100 ASA_ARAM_TC_REG [expr [dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x04] -dict set regsC100 ASA_ARAM_TC_CR_REG [expr [dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x08] -dict set regsC100 ASA_ARAM_STAT_REG [expr [dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x0C] +dict set regsC100 ASA_ARAM_PRI_REG [expr {[dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x00}] +dict set regsC100 ASA_ARAM_TC_REG [expr {[dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x04}] +dict set regsC100 ASA_ARAM_TC_CR_REG [expr {[dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x08}] +dict set regsC100 ASA_ARAM_STAT_REG [expr {[dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x0C}] -dict set regsC100 ASA_EBUS_PRI_REG [expr [dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x00] -dict set regsC100 ASA_EBUS_TC_REG [expr [dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x04] -dict set regsC100 ASA_EBUS_TC_CR_REG [expr [dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x08] -dict set regsC100 ASA_EBUS_STAT_REG [expr [dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x0C] +dict set regsC100 ASA_EBUS_PRI_REG [expr {[dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x00}] +dict set regsC100 ASA_EBUS_TC_REG [expr {[dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x04}] +dict set regsC100 ASA_EBUS_TC_CR_REG [expr {[dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x08}] +dict set regsC100 ASA_EBUS_STAT_REG [expr {[dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x0C}] dict set regsC100 IDMA_MASTER 0 dict set regsC100 TDMA_MASTER 1 @@ -87,16 +87,16 @@ dict set regsC100 MDMA_MASTER 5 #define ARM1_PRIORITY(level) (level << 16) #define MDMA_PRIORITY(level) (level << 20) -dict set regsC100 ASA_TC_REQIDMAEN [expr 1<<18] -dict set regsC100 ASA_TC_REQTDMEN [expr 1<<19] -dict set regsC100 ASA_TC_REQIPSECUSBEN [expr 1<<20] -dict set regsC100 ASA_TC_REQARM0EN [expr 1<<21] -dict set regsC100 ASA_TC_REQARM1EN [expr 1<<22] -dict set regsC100 ASA_TC_REQMDMAEN [expr 1<<23] +dict set regsC100 ASA_TC_REQIDMAEN [expr {1<<18}] +dict set regsC100 ASA_TC_REQTDMEN [expr {1<<19}] +dict set regsC100 ASA_TC_REQIPSECUSBEN [expr {1<<20}] +dict set regsC100 ASA_TC_REQARM0EN [expr {1<<21}] +dict set regsC100 ASA_TC_REQARM1EN [expr {1<<22}] +dict set regsC100 ASA_TC_REQMDMAEN [expr {1<<23}] dict set regsC100 MEMORY_BASE_ADDR 0x80000000 -dict set regsC100 MEMORY_MAX_ADDR [expr [dict get $regsC100 ASD_BASEADDR ] + 0x10] -dict set regsC100 MEMORY_CR [expr [dict get $regsC100 ASD_BASEADDR ] + 0x14] +dict set regsC100 MEMORY_MAX_ADDR [expr {[dict get $regsC100 ASD_BASEADDR ] + 0x10}] +dict set regsC100 MEMORY_CR [expr {[dict get $regsC100 ASD_BASEADDR ] + 0x14}] dict set regsC100 ROM_REMAP_EN 0x1 #define HAL_asb_priority(level) \ @@ -115,33 +115,33 @@ dict set regsC100 ROM_REMAP_EN 0x1 #// INTC block // #//////////////////////////////////////////////////////////// -dict set regsC100 INTC_ARM1_CONTROL_REG [expr [dict get $regsC100 INTC_BASEADDR ] + 0x18] +dict set regsC100 INTC_ARM1_CONTROL_REG [expr {[dict get $regsC100 INTC_BASEADDR ] + 0x18}] #//////////////////////////////////////////////////////////// #// TIMER block // #//////////////////////////////////////////////////////////// -dict set regsC100 TIMER0_CNTR_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x00] -dict set regsC100 TIMER0_CURR_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x04] -dict set regsC100 TIMER1_CNTR_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x08] -dict set regsC100 TIMER1_CURR_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x0C] +dict set regsC100 TIMER0_CNTR_REG [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x00}] +dict set regsC100 TIMER0_CURR_COUNT [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x04}] +dict set regsC100 TIMER1_CNTR_REG [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x08}] +dict set regsC100 TIMER1_CURR_COUNT [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x0C}] -dict set regsC100 TIMER2_CNTR_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x18] -dict set regsC100 TIMER2_LBOUND_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x10] -dict set regsC100 TIMER2_HBOUND_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x14] -dict set regsC100 TIMER2_CURR_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x1C] +dict set regsC100 TIMER2_CNTR_REG [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x18}] +dict set regsC100 TIMER2_LBOUND_REG [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x10}] +dict set regsC100 TIMER2_HBOUND_REG [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x14}] +dict set regsC100 TIMER2_CURR_COUNT [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x1C}] -dict set regsC100 TIMER3_LOBND [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x20] -dict set regsC100 TIMER3_HIBND [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x24] -dict set regsC100 TIMER3_CTRL [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x28] -dict set regsC100 TIMER3_CURR_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x2C] +dict set regsC100 TIMER3_LOBND [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x20}] +dict set regsC100 TIMER3_HIBND [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x24}] +dict set regsC100 TIMER3_CTRL [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x28}] +dict set regsC100 TIMER3_CURR_COUNT [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x2C}] -dict set regsC100 TIMER_MASK [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x40] -dict set regsC100 TIMER_STATUS [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x50] -dict set regsC100 TIMER_ACK [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x50] -dict set regsC100 TIMER_WDT_HIGH_BOUND [expr [dict get $regsC100 TIMER_BASEADDR ] + 0xD0] -dict set regsC100 TIMER_WDT_CONTROL [expr [dict get $regsC100 TIMER_BASEADDR ] + 0xD4] -dict set regsC100 TIMER_WDT_CURRENT_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0xD8] +dict set regsC100 TIMER_MASK [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x40}] +dict set regsC100 TIMER_STATUS [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x50}] +dict set regsC100 TIMER_ACK [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x50}] +dict set regsC100 TIMER_WDT_HIGH_BOUND [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0xD0}] +dict set regsC100 TIMER_WDT_CONTROL [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0xD4}] +dict set regsC100 TIMER_WDT_CURRENT_COUNT [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0xD8}] @@ -149,40 +149,40 @@ dict set regsC100 TIMER_WDT_CURRENT_COUNT [expr [dict get $regsC100 TIMER_BASEAD #// EBUS block #//////////////////////////////////////////////////////////// -dict set regsC100 EX_SWRST_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x00] -dict set regsC100 EX_CSEN_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x04] -dict set regsC100 EX_CS0_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x08] -dict set regsC100 EX_CS1_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x0C] -dict set regsC100 EX_CS2_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x10] -dict set regsC100 EX_CS3_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x14] -dict set regsC100 EX_CS4_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x18] -dict set regsC100 EX_CS0_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x1C] -dict set regsC100 EX_CS1_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x20] -dict set regsC100 EX_CS2_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x24] -dict set regsC100 EX_CS3_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x28] -dict set regsC100 EX_CS4_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x2C] -dict set regsC100 EX_CS0_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x30] -dict set regsC100 EX_CS1_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x34] -dict set regsC100 EX_CS2_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x38] -dict set regsC100 EX_CS3_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x3C] -dict set regsC100 EX_CS4_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x40] -dict set regsC100 EX_CS0_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x44] -dict set regsC100 EX_CS1_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x48] -dict set regsC100 EX_CS2_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x4C] -dict set regsC100 EX_CS3_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x50] -dict set regsC100 EX_CS4_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x54] -dict set regsC100 EX_CS0_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x58] -dict set regsC100 EX_CS1_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x5C] -dict set regsC100 EX_CS2_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x60] -dict set regsC100 EX_CS3_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x64] -dict set regsC100 EX_CS4_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x68] -dict set regsC100 EX_CLOCK_DIV_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x6C] - -dict set regsC100 EX_MFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x100] -dict set regsC100 EX_MFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x100] -dict set regsC100 EX_CSFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x104] -dict set regsC100 EX_WRFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x108] -dict set regsC100 EX_RDFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x10C] +dict set regsC100 EX_SWRST_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x00}] +dict set regsC100 EX_CSEN_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x04}] +dict set regsC100 EX_CS0_SEG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x08}] +dict set regsC100 EX_CS1_SEG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x0C}] +dict set regsC100 EX_CS2_SEG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x10}] +dict set regsC100 EX_CS3_SEG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x14}] +dict set regsC100 EX_CS4_SEG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x18}] +dict set regsC100 EX_CS0_CFG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x1C}] +dict set regsC100 EX_CS1_CFG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x20}] +dict set regsC100 EX_CS2_CFG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x24}] +dict set regsC100 EX_CS3_CFG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x28}] +dict set regsC100 EX_CS4_CFG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x2C}] +dict set regsC100 EX_CS0_TMG1_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x30}] +dict set regsC100 EX_CS1_TMG1_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x34}] +dict set regsC100 EX_CS2_TMG1_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x38}] +dict set regsC100 EX_CS3_TMG1_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x3C}] +dict set regsC100 EX_CS4_TMG1_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x40}] +dict set regsC100 EX_CS0_TMG2_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x44}] +dict set regsC100 EX_CS1_TMG2_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x48}] +dict set regsC100 EX_CS2_TMG2_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x4C}] +dict set regsC100 EX_CS3_TMG2_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x50}] +dict set regsC100 EX_CS4_TMG2_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x54}] +dict set regsC100 EX_CS0_TMG3_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x58}] +dict set regsC100 EX_CS1_TMG3_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x5C}] +dict set regsC100 EX_CS2_TMG3_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x60}] +dict set regsC100 EX_CS3_TMG3_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x64}] +dict set regsC100 EX_CS4_TMG3_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x68}] +dict set regsC100 EX_CLOCK_DIV_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x6C}] + +dict set regsC100 EX_MFSM_REG [expr {[dict get $regsC100 EBUS_BASEADDR] + 0x100}] +dict set regsC100 EX_MFSM_REG [expr {[dict get $regsC100 EBUS_BASEADDR] + 0x100}] +dict set regsC100 EX_CSFSM_REG [expr {[dict get $regsC100 EBUS_BASEADDR] + 0x104}] +dict set regsC100 EX_WRFSM_REG [expr {[dict get $regsC100 EBUS_BASEADDR] + 0x108}] +dict set regsC100 EX_RDFSM_REG [expr {[dict get $regsC100 EBUS_BASEADDR] + 0x10C}] dict set regsC100 EX_CLK_EN 0x00000001 @@ -211,21 +211,21 @@ dict set regsC100 EX_RDY_EDGE 0x00000800 #//////////////////////////////////////////////////////////// # GPIO outputs register -dict set regsC100 GPIO_OUTPUT_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x00] +dict set regsC100 GPIO_OUTPUT_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x00}] # GPIO Output Enable register -dict set regsC100 GPIO_OE_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x04] -dict set regsC100 GPIO_HI_INT_ENABLE_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x08] -dict set regsC100 GPIO_LO_INT_ENABLE_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x0C] +dict set regsC100 GPIO_OE_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x04}] +dict set regsC100 GPIO_HI_INT_ENABLE_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x08}] +dict set regsC100 GPIO_LO_INT_ENABLE_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x0C}] # GPIO input register -dict set regsC100 GPIO_INPUT_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x10] -dict set regsC100 APB_ACCESS_WS_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x14] -dict set regsC100 MUX_CONF_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x18] -dict set regsC100 SYSCONF_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x1C] -dict set regsC100 GPIO_ARM_ID_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x30] -dict set regsC100 GPIO_BOOTSTRAP_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x40] -dict set regsC100 GPIO_LOCK_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x38] -dict set regsC100 GPIO_IOCTRL_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x44] -dict set regsC100 GPIO_DEVID_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x50] +dict set regsC100 GPIO_INPUT_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x10}] +dict set regsC100 APB_ACCESS_WS_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x14}] +dict set regsC100 MUX_CONF_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x18}] +dict set regsC100 SYSCONF_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x1C}] +dict set regsC100 GPIO_ARM_ID_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x30}] +dict set regsC100 GPIO_BOOTSTRAP_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x40}] +dict set regsC100 GPIO_LOCK_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x38}] +dict set regsC100 GPIO_IOCTRL_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x44}] +dict set regsC100 GPIO_DEVID_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x50}] dict set regsC100 GPIO_IOCTRL_A15A16 0x00000001 dict set regsC100 GPIO_IOCTRL_A17A18 0x00000002 @@ -258,31 +258,31 @@ dict set regsC100 GPIO_BOTH_EDGES 3 #// UART #//////////////////////////////////////////////////////////// -dict set regsC100 UART0_RBR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x00] -dict set regsC100 UART0_THR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x00] -dict set regsC100 UART0_DLL [expr [dict get $regsC100 UART0_BASEADDR ] + 0x00] -dict set regsC100 UART0_IER [expr [dict get $regsC100 UART0_BASEADDR ] + 0x04] -dict set regsC100 UART0_DLH [expr [dict get $regsC100 UART0_BASEADDR ] + 0x04] -dict set regsC100 UART0_IIR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x08] -dict set regsC100 UART0_FCR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x08] -dict set regsC100 UART0_LCR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x0C] -dict set regsC100 UART0_MCR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x10] -dict set regsC100 UART0_LSR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x14] -dict set regsC100 UART0_MSR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x18] -dict set regsC100 UART0_SCR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x1C] - -dict set regsC100 UART1_RBR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x00] -dict set regsC100 UART1_THR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x00] -dict set regsC100 UART1_DLL [expr [dict get $regsC100 UART1_BASEADDR ] + 0x00] -dict set regsC100 UART1_IER [expr [dict get $regsC100 UART1_BASEADDR ] + 0x04] -dict set regsC100 UART1_DLH [expr [dict get $regsC100 UART1_BASEADDR ] + 0x04] -dict set regsC100 UART1_IIR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x08] -dict set regsC100 UART1_FCR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x08] -dict set regsC100 UART1_LCR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x0C] -dict set regsC100 UART1_MCR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x10] -dict set regsC100 UART1_LSR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x14] -dict set regsC100 UART1_MSR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x18] -dict set regsC100 UART1_SCR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x1C] +dict set regsC100 UART0_RBR [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x00}] +dict set regsC100 UART0_THR [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x00}] +dict set regsC100 UART0_DLL [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x00}] +dict set regsC100 UART0_IER [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x04}] +dict set regsC100 UART0_DLH [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x04}] +dict set regsC100 UART0_IIR [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x08}] +dict set regsC100 UART0_FCR [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x08}] +dict set regsC100 UART0_LCR [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x0C}] +dict set regsC100 UART0_MCR [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x10}] +dict set regsC100 UART0_LSR [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x14}] +dict set regsC100 UART0_MSR [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x18}] +dict set regsC100 UART0_SCR [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x1C}] + +dict set regsC100 UART1_RBR [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x00}] +dict set regsC100 UART1_THR [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x00}] +dict set regsC100 UART1_DLL [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x00}] +dict set regsC100 UART1_IER [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x04}] +dict set regsC100 UART1_DLH [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x04}] +dict set regsC100 UART1_IIR [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x08}] +dict set regsC100 UART1_FCR [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x08}] +dict set regsC100 UART1_LCR [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x0C}] +dict set regsC100 UART1_MCR [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x10}] +dict set regsC100 UART1_LSR [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x14}] +dict set regsC100 UART1_MSR [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x18}] +dict set regsC100 UART1_SCR [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x1C}] # /* default */ dict set regsC100 LCR_CHAR_LEN_5 0x00 @@ -308,51 +308,51 @@ dict set regsC100 LCR_PSB 0x80 dict set regsC100 LCR_DLAB 0x80 #/* FIFO Error Status */ -dict set regsC100 LSR_FIFOE [expr 1 << 7] +dict set regsC100 LSR_FIFOE [expr {1 << 7}] #/* Transmitter Empty */ -dict set regsC100 LSR_TEMT [expr 1 << 6] +dict set regsC100 LSR_TEMT [expr {1 << 6}] #/* Transmit Data Request */ -dict set regsC100 LSR_TDRQ [expr 1 << 5] +dict set regsC100 LSR_TDRQ [expr {1 << 5}] #/* Break Interrupt */ -dict set regsC100 LSR_BI [expr 1 << 4] +dict set regsC100 LSR_BI [expr {1 << 4}] #/* Framing Error */ -dict set regsC100 LSR_FE [expr 1 << 3] +dict set regsC100 LSR_FE [expr {1 << 3}] #/* Parity Error */ -dict set regsC100 LSR_PE [expr 1 << 2] +dict set regsC100 LSR_PE [expr {1 << 2}] #/* Overrun Error */ -dict set regsC100 LSR_OE [expr 1 << 1] +dict set regsC100 LSR_OE [expr {1 << 1}] #/* Data Ready */ -dict set regsC100 LSR_DR [expr 1 << 0] +dict set regsC100 LSR_DR [expr {1 << 0}] #/* DMA Requests Enable */ -dict set regsC100 IER_DMAE [expr 1 << 7] +dict set regsC100 IER_DMAE [expr {1 << 7}] #/* UART Unit Enable */ -dict set regsC100 IER_UUE [expr 1 << 6] +dict set regsC100 IER_UUE [expr {1 << 6}] #/* NRZ coding Enable */ -dict set regsC100 IER_NRZE [expr 1 << 5] +dict set regsC100 IER_NRZE [expr {1 << 5}] #/* Receiver Time Out Interrupt Enable */ -dict set regsC100 IER_RTIOE [expr 1 << 4] +dict set regsC100 IER_RTIOE [expr {1 << 4}] #/* Modem Interrupt Enable */ -dict set regsC100 IER_MIE [expr 1 << 3] +dict set regsC100 IER_MIE [expr {1 << 3}] #/* Receiver Line Status Interrupt Enable */ -dict set regsC100 IER_RLSE [expr 1 << 2] +dict set regsC100 IER_RLSE [expr {1 << 2}] #/* Transmit Data request Interrupt Enable */ -dict set regsC100 IER_TIE [expr 1 << 1] +dict set regsC100 IER_TIE [expr {1 << 1}] #/* Receiver Data Available Interrupt Enable */ -dict set regsC100 IER_RAVIE [expr 1 << 0] +dict set regsC100 IER_RAVIE [expr {1 << 0}] #/* FIFO Mode Enable Status */ -dict set regsC100 IIR_FIFOES1 [expr 1 << 7] +dict set regsC100 IIR_FIFOES1 [expr {1 << 7}] #/* FIFO Mode Enable Status */ -dict set regsC100 IIR_FIFOES0 [expr 1 << 6] +dict set regsC100 IIR_FIFOES0 [expr {1 << 6}] #/* Time Out Detected */ -dict set regsC100 IIR_TOD [expr 1 << 3] +dict set regsC100 IIR_TOD [expr {1 << 3}] #/* Interrupt Source Encoded */ -dict set regsC100 IIR_IID2 [expr 1 << 2] +dict set regsC100 IIR_IID2 [expr {1 << 2}] #/* Interrupt Source Encoded */ -dict set regsC100 IIR_IID1 [expr 1 << 1] +dict set regsC100 IIR_IID1 [expr {1 << 1}] #/* Interrupt Pending (active low) */ -dict set regsC100 IIR_IP [expr 1 << 0] +dict set regsC100 IIR_IP [expr {1 << 0}] #/* UART 16550 FIFO Control Register */ dict set regsC100 FCR_FIFOEN 0x01 @@ -372,17 +372,17 @@ dict set regsC100 IER_TXTH 0x02 #// CLK + RESET block #//////////////////////////////////////////////////////////// -dict set regsC100 CLKCORE_ARM_CLK_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x00] -dict set regsC100 CLKCORE_AHB_CLK_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x04] -dict set regsC100 CLKCORE_PLL_STATUS [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x08] -dict set regsC100 CLKCORE_CLKDIV_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x0C] -dict set regsC100 CLKCORE_TDM_CLK_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x10] -dict set regsC100 CLKCORE_FSYNC_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x14] -dict set regsC100 CLKCORE_CLK_PWR_DWN [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x18] -dict set regsC100 CLKCORE_RNG_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x1C] -dict set regsC100 CLKCORE_RNG_STATUS [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x20] -dict set regsC100 CLKCORE_ARM_CLK_CNTRL2 [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x24] -dict set regsC100 CLKCORE_TDM_REF_DIV_RST [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x40] +dict set regsC100 CLKCORE_ARM_CLK_CNTRL [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x00}] +dict set regsC100 CLKCORE_AHB_CLK_CNTRL [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x04}] +dict set regsC100 CLKCORE_PLL_STATUS [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x08}] +dict set regsC100 CLKCORE_CLKDIV_CNTRL [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x0C}] +dict set regsC100 CLKCORE_TDM_CLK_CNTRL [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x10}] +dict set regsC100 CLKCORE_FSYNC_CNTRL [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x14}] +dict set regsC100 CLKCORE_CLK_PWR_DWN [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x18}] +dict set regsC100 CLKCORE_RNG_CNTRL [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x1C}] +dict set regsC100 CLKCORE_RNG_STATUS [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x20}] +dict set regsC100 CLKCORE_ARM_CLK_CNTRL2 [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x24}] +dict set regsC100 CLKCORE_TDM_REF_DIV_RST [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x40}] dict set regsC100 ARM_PLL_BY_CTRL 0x80000000 dict set regsC100 ARM_AHB_BYP 0x04000000 @@ -429,8 +429,8 @@ dict set regsC100 FCLK_PLL_LOCK 0x00000001 #// reset block -dict set regsC100 BLOCK_RESET_REG [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x100] -dict set regsC100 CSP_RESET_REG [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x104] +dict set regsC100 BLOCK_RESET_REG [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x100}] +dict set regsC100 CSP_RESET_REG [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x104}] dict set regsC100 RNG_RST 0x1000 dict set regsC100 IPSEC_RST 0x0800 @@ -451,42 +451,42 @@ dict set regsC100 PCI_RST 0x0001 #//////////////////////////////////////////////////////////////// dict set regsC100 DDR_CONFIG_BASEADDR 0x0D000000 -dict set regsC100 DENALI_CTL_00_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x00] -dict set regsC100 DENALI_CTL_01_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x08] -dict set regsC100 DENALI_CTL_02_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x10] -dict set regsC100 DENALI_CTL_03_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x18] -dict set regsC100 DENALI_CTL_04_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x20] -dict set regsC100 DENALI_CTL_05_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x28] -dict set regsC100 DENALI_CTL_06_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x30] -dict set regsC100 DENALI_CTL_07_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x38] -dict set regsC100 DENALI_CTL_08_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x40] -dict set regsC100 DENALI_CTL_09_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x48] -dict set regsC100 DENALI_CTL_10_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x50] -dict set regsC100 DENALI_CTL_11_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x58] -dict set regsC100 DENALI_CTL_12_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x60] -dict set regsC100 DENALI_CTL_13_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x68] -dict set regsC100 DENALI_CTL_14_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x70] -dict set regsC100 DENALI_CTL_15_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x78] -dict set regsC100 DENALI_CTL_16_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x80] -dict set regsC100 DENALI_CTL_17_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x88] -dict set regsC100 DENALI_CTL_18_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x90] -dict set regsC100 DENALI_CTL_19_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x98] -dict set regsC100 DENALI_CTL_20_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0xA0] +dict set regsC100 DENALI_CTL_00_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x00}] +dict set regsC100 DENALI_CTL_01_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x08}] +dict set regsC100 DENALI_CTL_02_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x10}] +dict set regsC100 DENALI_CTL_03_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x18}] +dict set regsC100 DENALI_CTL_04_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x20}] +dict set regsC100 DENALI_CTL_05_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x28}] +dict set regsC100 DENALI_CTL_06_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x30}] +dict set regsC100 DENALI_CTL_07_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x38}] +dict set regsC100 DENALI_CTL_08_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x40}] +dict set regsC100 DENALI_CTL_09_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x48}] +dict set regsC100 DENALI_CTL_10_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x50}] +dict set regsC100 DENALI_CTL_11_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x58}] +dict set regsC100 DENALI_CTL_12_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x60}] +dict set regsC100 DENALI_CTL_13_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x68}] +dict set regsC100 DENALI_CTL_14_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x70}] +dict set regsC100 DENALI_CTL_15_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x78}] +dict set regsC100 DENALI_CTL_16_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x80}] +dict set regsC100 DENALI_CTL_17_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x88}] +dict set regsC100 DENALI_CTL_18_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x90}] +dict set regsC100 DENALI_CTL_19_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x98}] +dict set regsC100 DENALI_CTL_20_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0xA0}] # 32-bit value -dict set regsC100 DENALI_READY_CHECK [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x44] +dict set regsC100 DENALI_READY_CHECK [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x44}] # 8-bit -dict set regsC100 DENALI_WR_DQS [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x5D] +dict set regsC100 DENALI_WR_DQS [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x5D}] # 8-bit -dict set regsC100 DENALI_DQS_OUT [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x5A] +dict set regsC100 DENALI_DQS_OUT [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x5A}] # 8-bit -dict set regsC100 DENALI_DQS_DELAY0 [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x4F] +dict set regsC100 DENALI_DQS_DELAY0 [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x4F}] # 8-bit -dict set regsC100 DENALI_DQS_DELAY1 [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x50] +dict set regsC100 DENALI_DQS_DELAY1 [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x50}] # 8-bit -dict set regsC100 DENALI_DQS_DELAY2 [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x51] +dict set regsC100 DENALI_DQS_DELAY2 [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x51}] # 8-bit -dict set regsC100 DENALI_DQS_DELAY3 [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x52] +dict set regsC100 DENALI_DQS_DELAY3 [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x52}] # end of proc regsC100 diff --git a/tcl/target/davinci.cfg b/tcl/target/davinci.cfg index 859a925..5ca54ae 100644 --- a/tcl/target/davinci.cfg +++ b/tcl/target/davinci.cfg @@ -4,7 +4,7 @@ # davinci_pinmux: assigns PINMUX$reg <== $value proc davinci_pinmux {soc reg value} { - mww [expr [dict get $soc sysbase] + 4 * $reg] $value + mww [expr {[dict get $soc sysbase] + 4 * $reg}] $value } source [find mem_helper.tcl] @@ -22,53 +22,53 @@ source [find mem_helper.tcl] # PLL version 0x02: tested on dm355 # REVISIT: On dm6446/dm357 the PLLRST polarity is different. proc pll_v02_setup {pll_addr mult config} { - set pll_ctrl_addr [expr $pll_addr + 0x100] + set pll_ctrl_addr [expr {$pll_addr + 0x100}] set pll_ctrl [mrw $pll_ctrl_addr] # 1 - clear CLKMODE (bit 8) iff using on-chip oscillator # NOTE: this assumes we should clear that bit - set pll_ctrl [expr $pll_ctrl & ~0x0100] + set pll_ctrl [expr {$pll_ctrl & ~0x0100}] mww $pll_ctrl_addr $pll_ctrl # 2 - clear PLLENSRC (bit 5) - set pll_ctrl [expr $pll_ctrl & ~0x0020] + set pll_ctrl [expr {$pll_ctrl & ~0x0020}] mww $pll_ctrl_addr $pll_ctrl # 3 - clear PLLEN (bit 0) ... enter bypass mode - set pll_ctrl [expr $pll_ctrl & ~0x0001] + set pll_ctrl [expr {$pll_ctrl & ~0x0001}] mww $pll_ctrl_addr $pll_ctrl # 4 - wait at least 4 refclk cycles sleep 1 # 5 - set PLLRST (bit 3) - set pll_ctrl [expr $pll_ctrl | 0x0008] + set pll_ctrl [expr {$pll_ctrl | 0x0008}] mww $pll_ctrl_addr $pll_ctrl # 6 - set PLLDIS (bit 4) - set pll_ctrl [expr $pll_ctrl | 0x0010] + set pll_ctrl [expr {$pll_ctrl | 0x0010}] mww $pll_ctrl_addr $pll_ctrl # 7 - clear PLLPWRDN (bit 1) - set pll_ctrl [expr $pll_ctrl & ~0x0002] + set pll_ctrl [expr {$pll_ctrl & ~0x0002}] mww $pll_ctrl_addr $pll_ctrl # 8 - clear PLLDIS (bit 4) - set pll_ctrl [expr $pll_ctrl & ~0x0010] + set pll_ctrl [expr {$pll_ctrl & ~0x0010}] mww $pll_ctrl_addr $pll_ctrl # 9 - optional: write prediv, postdiv, and pllm # NOTE: for dm355 PLL1, postdiv is controlled via MISC register - mww [expr $pll_addr + 0x0110] [expr ($mult - 1) & 0xff] + mww [expr {$pll_addr + 0x0110}] [expr {($mult - 1) & 0xff}] if { [dict exists $config prediv] } { set div [dict get $config prediv] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0114] $div + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0114}] $div } if { [dict exists $config postdiv] } { set div [dict get $config postdiv] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0128] $div + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0128}] $div } # 10 - optional: set plldiv1, plldiv2, ... @@ -78,47 +78,47 @@ proc pll_v02_setup {pll_addr mult config} { set go 0 if { [dict exists $config div1] } { set div [dict get $config div1] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0118] $div + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0118}] $div set go 1 } if { [dict exists $config div2] } { set div [dict get $config div2] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x011c] $div + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x011c}] $div set go 1 } if { [dict exists $config div3] } { set div [dict get $config div3] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0120] $div + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0120}] $div set go 1 } if { [dict exists $config div4] } { set div [dict get $config div4] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0160] $div + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0160}] $div set go 1 } if { [dict exists $config div5] } { set div [dict get $config div5] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0164] $div + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0164}] $div set go 1 } if {$go != 0} { # write pllcmd.GO; poll pllstat.GO - mww [expr $pll_addr + 0x0138] 0x01 - set pllstat [expr $pll_addr + 0x013c] - while {[expr [mrw $pllstat] & 0x01] != 0} { sleep 1 } + mww [expr {$pll_addr + 0x0138}] 0x01 + set pllstat [expr {$pll_addr + 0x013c}] + while {[expr {[mrw $pllstat] & 0x01}] != 0} { sleep 1 } } - mww [expr $pll_addr + 0x0138] 0x00 + mww [expr {$pll_addr + 0x0138}] 0x00 # 11 - wait at least 5 usec for reset to finish # (assume covered by overheads including JTAG messaging) # 12 - clear PLLRST (bit 3) - set pll_ctrl [expr $pll_ctrl & ~0x0008] + set pll_ctrl [expr {$pll_ctrl & ~0x0008}] mww $pll_ctrl_addr $pll_ctrl # 13 - wait at least 8000 refclk cycles for PLL to lock @@ -126,53 +126,53 @@ proc pll_v02_setup {pll_addr mult config} { sleep 3 # 14 - set PLLEN (bit 0) ... leave bypass mode - set pll_ctrl [expr $pll_ctrl | 0x0001] + set pll_ctrl [expr {$pll_ctrl | 0x0001}] mww $pll_ctrl_addr $pll_ctrl } # PLL version 0x03: tested on dm365 proc pll_v03_setup {pll_addr mult config} { - set pll_ctrl_addr [expr $pll_addr + 0x100] - set pll_secctrl_addr [expr $pll_addr + 0x108] + set pll_ctrl_addr [expr {$pll_addr + 0x100}] + set pll_secctrl_addr [expr {$pll_addr + 0x108}] set pll_ctrl [mrw $pll_ctrl_addr] # 1 - power up the PLL - set pll_ctrl [expr $pll_ctrl & ~0x0002] + set pll_ctrl [expr {$pll_ctrl & ~0x0002}] mww $pll_ctrl_addr $pll_ctrl # 2 - clear PLLENSRC (bit 5) - set pll_ctrl [expr $pll_ctrl & ~0x0020] + set pll_ctrl [expr {$pll_ctrl & ~0x0020}] mww $pll_ctrl_addr $pll_ctrl # 2 - clear PLLEN (bit 0) ... enter bypass mode - set pll_ctrl [expr $pll_ctrl & ~0x0001] + set pll_ctrl [expr {$pll_ctrl & ~0x0001}] mww $pll_ctrl_addr $pll_ctrl # 3 - wait at least 4 refclk cycles sleep 1 # 4 - set PLLRST (bit 3) - set pll_ctrl [expr $pll_ctrl | 0x0008] + set pll_ctrl [expr {$pll_ctrl | 0x0008}] mww $pll_ctrl_addr $pll_ctrl # 5 - wait at least 5 usec sleep 1 # 6 - clear PLLRST (bit 3) - set pll_ctrl [expr $pll_ctrl & ~0x0008] + set pll_ctrl [expr {$pll_ctrl & ~0x0008}] mww $pll_ctrl_addr $pll_ctrl # 9 - optional: write prediv, postdiv, and pllm - mww [expr $pll_addr + 0x0110] [expr ($mult / 2) & 0x1ff] + mww [expr {$pll_addr + 0x0110}] [expr {($mult / 2) & 0x1ff}] if { [dict exists $config prediv] } { set div [dict get $config prediv] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0114] $div + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0114}] $div } if { [dict exists $config postdiv] } { set div [dict get $config postdiv] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0128] $div + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0128}] $div } # 10 - write start sequence to PLLSECCTL @@ -187,99 +187,99 @@ proc pll_v03_setup {pll_addr mult config} { set aln 0 if { [dict exists $config div1] } { set div [dict get $config div1] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0118] $div - set aln [expr $aln | 0x1] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0118}] $div + set aln [expr {$aln | 0x1}] } else { - mww [expr $pll_addr + 0x0118] 0 + mww [expr {$pll_addr + 0x0118}] 0 } if { [dict exists $config div2] } { set div [dict get $config div2] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x011c] $div - set aln [expr $aln | 0x2] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x011c}] $div + set aln [expr {$aln | 0x2}] } else { - mww [expr $pll_addr + 0x011c] 0 + mww [expr {$pll_addr + 0x011c}] 0 } if { [dict exists $config div3] } { set div [dict get $config div3] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0120] $div - set aln [expr $aln | 0x4] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0120}] $div + set aln [expr {$aln | 0x4}] } else { - mww [expr $pll_addr + 0x0120] 0 + mww [expr {$pll_addr + 0x0120}] 0 } if { [dict exists $config oscdiv] } { set div [dict get $config oscdiv] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0124] $div + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0124}] $div } else { - mww [expr $pll_addr + 0x0124] 0 + mww [expr {$pll_addr + 0x0124}] 0 } if { [dict exists $config div4] } { set div [dict get $config div4] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0160] $div - set aln [expr $aln | 0x8] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0160}] $div + set aln [expr {$aln | 0x8}] } else { - mww [expr $pll_addr + 0x0160] 0 + mww [expr {$pll_addr + 0x0160}] 0 } if { [dict exists $config div5] } { set div [dict get $config div5] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0164] $div - set aln [expr $aln | 0x10] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0164}] $div + set aln [expr {$aln | 0x10}] } else { - mww [expr $pll_addr + 0x0164] 0 + mww [expr {$pll_addr + 0x0164}] 0 } if { [dict exists $config div6] } { set div [dict get $config div6] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0168] $div - set aln [expr $aln | 0x20] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0168}] $div + set aln [expr {$aln | 0x20}] } else { - mww [expr $pll_addr + 0x0168] 0 + mww [expr {$pll_addr + 0x0168}] 0 } if { [dict exists $config div7] } { set div [dict get $config div7] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x016c] $div - set aln [expr $aln | 0x40] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x016c}] $div + set aln [expr {$aln | 0x40}] } else { - mww [expr $pll_addr + 0x016c] 0 + mww [expr {$pll_addr + 0x016c}] 0 } if { [dict exists $config div8] } { set div [dict get $config div8] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0170] $div - set aln [expr $aln | 0x80] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0170}] $div + set aln [expr {$aln | 0x80}] } else { - mww [expr $pll_addr + 0x0170] 0 + mww [expr {$pll_addr + 0x0170}] 0 } if { [dict exists $config div9] } { set div [dict get $config div9] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0174] $div - set aln [expr $aln | 0x100] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0174}] $div + set aln [expr {$aln | 0x100}] } else { - mww [expr $pll_addr + 0x0174] 0 + mww [expr {$pll_addr + 0x0174}] 0 } if {$aln != 0} { # clear pllcmd.GO - mww [expr $pll_addr + 0x0138] 0x00 - # write alingment flags - mww [expr $pll_addr + 0x0140] $aln + mww [expr {$pll_addr + 0x0138}] 0x00 + # write alignment flags + mww [expr {$pll_addr + 0x0140}] $aln # write pllcmd.GO; poll pllstat.GO - mww [expr $pll_addr + 0x0138] 0x01 - set pllstat [expr $pll_addr + 0x013c] - while {[expr [mrw $pllstat] & 0x01] != 0} { sleep 1 } + mww [expr {$pll_addr + 0x0138}] 0x01 + set pllstat [expr {$pll_addr + 0x013c}] + while {[expr {[mrw $pllstat] & 0x01}] != 0} { sleep 1 } } - mww [expr $pll_addr + 0x0138] 0x00 + mww [expr {$pll_addr + 0x0138}] 0x00 set addr [dict get $config ctladdr] - while {[expr [mrw $addr] & 0x0e000000] != 0x0e000000} { sleep 1 } + while {[expr {[mrw $addr] & 0x0e000000}] != 0x0e000000} { sleep 1 } # 12 - set PLLEN (bit 0) ... leave bypass mode - set pll_ctrl [expr $pll_ctrl | 0x0001] + set pll_ctrl [expr {$pll_ctrl | 0x0001}] mww $pll_ctrl_addr $pll_ctrl } @@ -290,29 +290,29 @@ proc pll_v03_setup {pll_addr mult config} { proc psc_enable {module} { set psc_addr 0x01c41000 # write MDCTL - mmw [expr $psc_addr + 0x0a00 + (4 * $module)] 0x03 0x1f + mmw [expr {$psc_addr + 0x0a00 + (4 * $module)}] 0x03 0x1f } # prepare a non-DSP module to be reset; finish with psc_go proc psc_reset {module} { set psc_addr 0x01c41000 # write MDCTL - mmw [expr $psc_addr + 0x0a00 + (4 * $module)] 0x01 0x1f + mmw [expr {$psc_addr + 0x0a00 + (4 * $module)}] 0x01 0x1f } # execute non-DSP PSC transition(s) set up by psc_enable, psc_reset, etc proc psc_go {} { set psc_addr 0x01c41000 - set ptstat_addr [expr $psc_addr + 0x0128] + set ptstat_addr [expr {$psc_addr + 0x0128}] # just in case PTSTAT.go isn't clear - while { [expr [mrw $ptstat_addr] & 0x01] != 0 } { sleep 1 } + while { [expr {[mrw $ptstat_addr] & 0x01}] != 0 } { sleep 1 } # write PTCMD.go ... ignoring any DSP power domain - mww [expr $psc_addr + 0x0120] 1 + mww [expr {$psc_addr + 0x0120}] 1 # wait for PTSTAT.go to clear (again ignoring DSP power domain) - while { [expr [mrw $ptstat_addr] & 0x01] != 0 } { sleep 1 } + while { [expr {[mrw $ptstat_addr] & 0x01}] != 0 } { sleep 1 } } # @@ -344,34 +344,34 @@ proc davinci_wdog_reset {} { # # EMUMGT_CLKSPEED: write FREE bit to run despite emulation halt - mww phys [expr $timer2_phys + 0x28] 0x00004000 + mww phys [expr {$timer2_phys + 0x28}] 0x00004000 # # Part II -- in case watchdog hasn't been set up # # TCR: disable, force internal clock source - mww phys [expr $timer2_phys + 0x20] 0 + mww phys [expr {$timer2_phys + 0x20}] 0 # TGCR: reset, force to 64-bit wdog mode, un-reset ("initial" state) - mww phys [expr $timer2_phys + 0x24] 0 - mww phys [expr $timer2_phys + 0x24] 0x110b + mww phys [expr {$timer2_phys + 0x24}] 0 + mww phys [expr {$timer2_phys + 0x24}] 0x110b # clear counter (TIM12, TIM34) and period (PRD12, PRD34) registers # so watchdog triggers ASAP - mww phys [expr $timer2_phys + 0x10] 0 - mww phys [expr $timer2_phys + 0x14] 0 - mww phys [expr $timer2_phys + 0x18] 0 - mww phys [expr $timer2_phys + 0x1c] 0 + mww phys [expr {$timer2_phys + 0x10}] 0 + mww phys [expr {$timer2_phys + 0x14}] 0 + mww phys [expr {$timer2_phys + 0x18}] 0 + mww phys [expr {$timer2_phys + 0x1c}] 0 # WDTCR: put into pre-active state, then active - mww phys [expr $timer2_phys + 0x28] 0xa5c64000 - mww phys [expr $timer2_phys + 0x28] 0xda7e4000 + mww phys [expr {$timer2_phys + 0x28}] 0xa5c64000 + mww phys [expr {$timer2_phys + 0x28}] 0xda7e4000 # # Part III -- it's ready to rumble # # WDTCR: write invalid WDKEY to trigger reset - mww phys [expr $timer2_phys + 0x28] 0x00004000 + mww phys [expr {$timer2_phys + 0x28}] 0x00004000 } diff --git a/tcl/target/fm4_mb9bf.cfg b/tcl/target/fm4_mb9bf.cfg index e53fdc8..ca4e5f9 100644 --- a/tcl/target/fm4_mb9bf.cfg +++ b/tcl/target/fm4_mb9bf.cfg @@ -11,7 +11,7 @@ if { [info exists WORKAREASIZE] } { set _WORKAREASIZE 0x8000 } -$_TARGETNAME configure -work-area-phys [expr 0x20000000 - $_WORKAREASIZE] \ +$_TARGETNAME configure -work-area-phys [expr {0x20000000 - $_WORKAREASIZE}] \ -work-area-size $_WORKAREASIZE -work-area-backup 0 set _FLASHNAME $_CHIPNAME.flash diff --git a/tcl/target/fm4_s6e2cc.cfg b/tcl/target/fm4_s6e2cc.cfg index 60b73b9..c6f835d 100644 --- a/tcl/target/fm4_s6e2cc.cfg +++ b/tcl/target/fm4_s6e2cc.cfg @@ -11,7 +11,7 @@ if { [info exists WORKAREASIZE] } { set _WORKAREASIZE 0x18000 } -$_TARGETNAME configure -work-area-phys [expr 0x20000000 - $_WORKAREASIZE] \ +$_TARGETNAME configure -work-area-phys [expr {0x20000000 - $_WORKAREASIZE}] \ -work-area-size $_WORKAREASIZE -work-area-backup 0 set _FLASHNAME $_CHIPNAME.flash diff --git a/tcl/target/hilscher_netx500.cfg b/tcl/target/hilscher_netx500.cfg index 93375fd..6d919f9 100644 --- a/tcl/target/hilscher_netx500.cfg +++ b/tcl/target/hilscher_netx500.cfg @@ -36,10 +36,10 @@ proc mread32 {addr} { proc sdram_fix { } { set accesskey [mread32 0x00100070] - mww 0x00100070 [expr $accesskey] + mww 0x00100070 $accesskey mww 0x0010002c 0x00000001 - if {[expr [mread32 0x0010002c] & 0x07] == 0x07} { + if {[expr {[mread32 0x0010002c] & 0x07}] == 0x07} { puts "SDRAM Fix was not executed. Probably your CPU halted too late and the register is already locked!" } else { puts "SDRAM Fix succeeded!" diff --git a/tcl/target/icepick.cfg b/tcl/target/icepick.cfg index d125071..cc824ad 100644 --- a/tcl/target/icepick.cfg +++ b/tcl/target/icepick.cfg @@ -54,8 +54,8 @@ proc icepick_c_disconnect {jrc} { proc icepick_c_router {jrc rw block register payload} { set new_dr_value \ - [expr ( ($rw & 0x1) << 31) | ( ($block & 0x7) << 28) | \ - ( ($register & 0xF) << 24) | ( $payload & 0xFFFFFF ) ] + [expr { ( ($rw & 0x1) << 31) | ( ($block & 0x7) << 28) | \ + ( ($register & 0xF) << 24) | ( $payload & 0xFFFFFF ) } ] # echo "\tNew router value:\t0x[format %x $new_dr_value]" @@ -84,7 +84,7 @@ proc icepick_c_tapenable {jrc port} { set block 0x2 } elseif { $port < 32 } { # Test tap - set tap [expr ($port - 16)] + set tap [expr {$port - 16}] set block 0x1 } else { echo "ERROR: Invalid ICEPick C port number: $port" diff --git a/tcl/target/imx.cfg b/tcl/target/imx.cfg index ccfddb6..e2bee7a 100644 --- a/tcl/target/imx.cfg +++ b/tcl/target/imx.cfg @@ -10,7 +10,7 @@ proc setc15 {regs value} { echo [format "set p15 0x%04x, 0x%08x" $regs $value] - arm mcr 15 [expr ($regs>>12)&0x7] [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] [expr ($regs>>8)&0x7] $value + arm mcr 15 [expr {($regs>>12)&0x7}] [expr {($regs>>0)&0xf}] [expr {($regs>>4)&0xf}] [expr {($regs>>8)&0x7}] $value } diff --git a/tcl/target/ixp42x.cfg b/tcl/target/ixp42x.cfg index 624fe29..ee10b21 100644 --- a/tcl/target/ixp42x.cfg +++ b/tcl/target/ixp42x.cfg @@ -72,11 +72,11 @@ proc ixp42x_init_sdram { SDRAM_CFG REFRESH CASLAT } { switch $CASLAT { 2 { - set SDRAM_CFG [expr $SDRAM_CFG | $::IXP42x_SDRAM_CL2 ] + set SDRAM_CFG [expr {$SDRAM_CFG | $::IXP42x_SDRAM_CL2} ] set CASCMD $::IXP425_SDRAM_IR_MODE_SET_CAS2_CMD } 3 { - set SDRAM_CFG [expr $SDRAM_CFG | $::IXP42x_SDRAM_CL3 ] + set SDRAM_CFG [expr {$SDRAM_CFG | $::IXP42x_SDRAM_CL3} ] set CASCMD $::IXP425_SDRAM_IR_MODE_SET_CAS3_CMD } default { error [format "unsupported cas latency \"%s\" " $CASLAT] } diff --git a/tcl/target/lpc8nxx.cfg b/tcl/target/lpc8nxx.cfg index 1bc77b2..4db78cb 100644 --- a/tcl/target/lpc8nxx.cfg +++ b/tcl/target/lpc8nxx.cfg @@ -56,7 +56,7 @@ proc set_sysclk_500khz {} { echo "Notice: sysclock set to 500kHz." } -# Do not remap the ARM interrupt vectors to anything but the beginning ot the flash. +# Do not remap the ARM interrupt vectors to anything but the beginning of the flash. # Table System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description # Bit Symbol Value Description # 0 map - interrupt vector remap. 0 after boot. diff --git a/tcl/target/omap4430.cfg b/tcl/target/omap4430.cfg index 6e3e78d..5b9e23c 100644 --- a/tcl/target/omap4430.cfg +++ b/tcl/target/omap4430.cfg @@ -91,7 +91,7 @@ set _TARGETNAME $_CHIPNAME.cpu # 0x80000000 | (coreid << CORTEX_A8_PADDRDBG_CPU_SHIFT) set _coreid 0 -set _dbgbase [expr 0x80000000 | ($_coreid << 13)] +set _dbgbase [expr {0x80000000 | ($_coreid << 13)}] echo "Using dbgbase = [format 0x%x $_dbgbase]" dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu diff --git a/tcl/target/omap4460.cfg b/tcl/target/omap4460.cfg index 218eb64..fb76e13 100644 --- a/tcl/target/omap4460.cfg +++ b/tcl/target/omap4460.cfg @@ -91,7 +91,7 @@ set _TARGETNAME $_CHIPNAME.cpu # 0x80000000 | (coreid << CORTEX_A8_PADDRDBG_CPU_SHIFT) set _coreid 0 -set _dbgbase [expr 0x80000000 | ($_coreid << 13)] +set _dbgbase [expr {0x80000000 | ($_coreid << 13)}] echo "Using dbgbase = [format 0x%x $_dbgbase]" dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu diff --git a/tcl/target/or1k.cfg b/tcl/target/or1k.cfg index 360a0dd..f85c2ee 100644 --- a/tcl/target/or1k.cfg +++ b/tcl/target/or1k.cfg @@ -69,4 +69,4 @@ set ENABLE_JSP_MULTI 4 # on burst reads and writes to improve download speeds. # This option must match the RTL configured option. -du_select adv [expr $ADBG_USE_HISPEED | $ENABLE_JSP_SERVER | $ENABLE_JSP_MULTI] +du_select adv [expr {$ADBG_USE_HISPEED | $ENABLE_JSP_SERVER | $ENABLE_JSP_MULTI}] diff --git a/tcl/target/pic32mx.cfg b/tcl/target/pic32mx.cfg index 51a6bbd..f15924f 100644 --- a/tcl/target/pic32mx.cfg +++ b/tcl/target/pic32mx.cfg @@ -42,7 +42,7 @@ target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_TARGETNAM global _PIC32MX_DATASIZE global _WORKAREASIZE set _PIC32MX_DATASIZE 0x800 -set _PIC32MX_PROGSIZE [expr ($_WORKAREASIZE - $_PIC32MX_DATASIZE)] +set _PIC32MX_PROGSIZE [expr {$_WORKAREASIZE - $_PIC32MX_DATASIZE}] $_TARGETNAME configure -work-area-phys 0xa0000800 -work-area-size $_PIC32MX_PROGSIZE -work-area-backup 0 $_TARGETNAME configure -event reset-init { diff --git a/tcl/target/psoc4.cfg b/tcl/target/psoc4.cfg index b568282..cffcbc7 100644 --- a/tcl/target/psoc4.cfg +++ b/tcl/target/psoc4.cfg @@ -60,7 +60,7 @@ adapter speed 1500 # # Newer families like PSoC 4000, 4100M, 4200M, 4100L, 4200L and PSoC 4 BLE # clear TEST_MODE flag during device reset so workaround is not possible. -# Use a KitProg adapter for theese devices or "reset halt" will not stop +# Use a KitProg adapter for these devices or "reset halt" will not stop # before executing user code. # # 3) SWD cannot be connected during system initialization after reset. @@ -78,18 +78,18 @@ proc psoc4_get_family_id {} { if { $err } { return 0 } - if { [expr $romtable_pid(0) & 0xffffff00 ] - || [expr $romtable_pid(1) & 0xffffff00 ] - || [expr $romtable_pid(2) & 0xffffff00 ] } { + if { [expr {$romtable_pid(0) & 0xffffff00 }] + || [expr {$romtable_pid(1) & 0xffffff00 }] + || [expr {$romtable_pid(2) & 0xffffff00 }] } { echo "Unexpected data in ROMTABLE" return 0 } - set designer_id [expr (( $romtable_pid(1) & 0xf0 ) >> 4) | (( $romtable_pid(2) & 0xf ) << 4 ) ] + set designer_id [expr {(( $romtable_pid(1) & 0xf0 ) >> 4) | (( $romtable_pid(2) & 0xf ) << 4 ) }] if { $designer_id != 0xb4 } { echo [format "ROMTABLE Designer ID 0x%02x is not Cypress" $designer_id] return 0 } - set family_id [expr ( $romtable_pid(0) & 0xff ) | (( $romtable_pid(1) & 0xf ) << 8 ) ] + set family_id [expr {( $romtable_pid(0) & 0xff ) | (( $romtable_pid(1) & 0xf ) << 8 ) }] return $family_id } @@ -194,7 +194,7 @@ proc ocd_process_reset_inner { MODE } { # Set registers to reset vector values mem2array value 32 0 2 - reg pc [expr $value(1) & 0xfffffffe ] + reg pc [expr {$value(1) & 0xfffffffe} ] reg msp $value(0) if { $PSOC4_TEST_MODE_WORKAROUND } { diff --git a/tcl/target/psoc5lp.cfg b/tcl/target/psoc5lp.cfg index b4e8d05..c90fd42 100644 --- a/tcl/target/psoc5lp.cfg +++ b/tcl/target/psoc5lp.cfg @@ -34,7 +34,7 @@ if { [info exists WORKAREASIZE] } { set _WORKAREASIZE 0x2000 } -$_TARGETNAME configure -work-area-phys [expr 0x20000000 - $_WORKAREASIZE / 2] \ +$_TARGETNAME configure -work-area-phys [expr {0x20000000 - $_WORKAREASIZE / 2}] \ -work-area-size $_WORKAREASIZE -work-area-backup 0 source [find mem_helper.tcl] @@ -43,15 +43,15 @@ $_TARGETNAME configure -event reset-init { # Configure Target Device (PSoC 5LP Device Programming Specification 5.2) set PANTHER_DBG_CFG 0x4008000C - set PANTHER_DBG_CFG_BYPASS [expr 1 << 1] + set PANTHER_DBG_CFG_BYPASS [expr {1 << 1}] mmw $PANTHER_DBG_CFG $PANTHER_DBG_CFG_BYPASS 0 set PM_ACT_CFG0 0x400043A0 mww $PM_ACT_CFG0 0xBF set FASTCLK_IMO_CR 0x40004200 - set FASTCLK_IMO_CR_F_RANGE_2 [expr 2 << 0] - set FASTCLK_IMO_CR_F_RANGE_MASK [expr 7 << 0] + set FASTCLK_IMO_CR_F_RANGE_2 [expr {2 << 0}] + set FASTCLK_IMO_CR_F_RANGE_MASK [expr {7 << 0}] mmw $FASTCLK_IMO_CR $FASTCLK_IMO_CR_F_RANGE_2 $FASTCLK_IMO_CR_F_RANGE_MASK } diff --git a/tcl/target/renesas_rz_g2.cfg b/tcl/target/renesas_rz_g2.cfg new file mode 100644 index 0000000..3615aa0 --- /dev/null +++ b/tcl/target/renesas_rz_g2.cfg @@ -0,0 +1,185 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Renesas RZ/G2 SOCs +# - There are a combination of Cortex-A57s, Cortex-A53s, Cortex-A55, Cortex-R7 +# and Cortex-M33 for each SOC +# - Each SOC can boot through the Cortex-A5x cores + +# Supported RZ/G2 SOCs and their cores: +# RZ/G2H: Cortex-A57 x4, Cortex-A53 x4, Cortex-R7 +# RZ/G2M: Cortex-A57 x2, Cortex-A53 x4, Cortex-R7 +# RZ/G2N: Cortex-A57 x2, Cortex-R7 +# RZ/G2E: Cortex-A53 x2, Cortex-R7 +# RZ/G2L: Cortex-A55 x2, Cortex-M33 + +# Usage: +# There are 2 configuration options: +# SOC: Selects the supported SOC. (Default 'G2L') +# BOOT_CORE: Selects the booting core. 'CA57', 'CA53' or 'CA55' + +transport select jtag +reset_config trst_and_srst srst_gates_jtag +adapter speed 4000 +adapter srst delay 500 + +if { [info exists SOC] } { + set _soc $SOC +} else { + set _soc G2L +} + +set _num_ca57 0 +set _num_ca55 0 +set _num_ca53 0 +set _num_cr7 0 +set _num_cm33 0 + +# Set configuration for each SOC and the default 'BOOT_CORE' +switch $_soc { + G2H { + set _CHIPNAME r8a774ex + set _num_ca57 4 + set _num_ca53 4 + set _num_cr7 1 + set _boot_core CA57 + set _ap_num 1 + } + G2M { + set _CHIPNAME r8a774ax + set _num_ca57 2 + set _num_ca53 4 + set _num_cr7 1 + set _boot_core CA57 + set _ap_num 1 + } + G2N { + set _CHIPNAME r8a774bx + set _num_ca57 2 + set _num_ca53 0 + set _num_cr7 1 + set _boot_core CA57 + set _ap_num 1 + } + G2E { + set _CHIPNAME r8a774c0 + set _num_ca57 0 + set _num_ca53 2 + set _num_cr7 1 + set _boot_core CA53 + set _ap_num 1 + } + G2L { + set _CHIPNAME r9a07g044l + set _num_ca55 2 + set _num_cm33 1 + set _boot_core CA55 + set _ap_num 0 + } + default { + error "'$_soc' is invalid!" + } +} + +# If configured, override the default 'CHIPNAME' +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} + +# If configured, override the default 'BOOT_CORE' +if { [info exists BOOT_CORE] } { + set _boot_core $BOOT_CORE +} + +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x6ba00477 +} + +echo "\t$_soc - $_num_ca57 CA57(s), $_num_ca55 CA55(s), $_num_ca53 CA53(s), $_num_cr7 CR7(s), \ + $_num_cm33 CM33(s)" +echo "\tBoot Core - $_boot_core\n" + +set _DAPNAME $_CHIPNAME.dap + + +# TAP and DAP +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID \ + -ignore-version +dap create $_DAPNAME -chain-position $_CHIPNAME.cpu +echo "$_CHIPNAME.cpu" + +set CA57_DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000} +set CA57_CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000} +set CA55_DBGBASE {0x10E10000 0x10F10000} +set CA55_CTIBASE {0x10E20000 0x10F20000} +set CA53_DBGBASE {0x80C10000 0x80D10000 0x80E10000 0x80F10000} +set CA53_CTIBASE {0x80C20000 0x80D20000 0x80E20000 0x80F20000} +set CR7_DBGBASE 0x80910000 +set CR7_CTIBASE 0x80918000 +set CM33_DBGBASE 0xE000E000 +set CM33_CTIBASE 0xE0042000 + +set smp_targets "" + +proc setup_a5x {core_name dbgbase ctibase num boot} { + for { set _core 0 } { $_core < $num } { incr _core } { + set _TARGETNAME $::_CHIPNAME.$core_name.$_core + set _CTINAME $_TARGETNAME.cti + cti create $_CTINAME -dap $::_DAPNAME -ap-num $::_ap_num \ + -baseaddr [lindex $ctibase $_core] + target create $_TARGETNAME aarch64 -dap $::_DAPNAME \ + -ap-num $::_ap_num -dbgbase [lindex $dbgbase $_core] -cti $_CTINAME + if { $_core > 0 || $boot == 0 } { + $_TARGETNAME configure -defer-examine + } + set ::smp_targets "$::smp_targets $_TARGETNAME" + } +} + +proc setup_cr7 {dbgbase ctibase} { + set _TARGETNAME $::_CHIPNAME.r7 + set _CTINAME $_TARGETNAME.cti + cti create $_CTINAME -dap $::_DAPNAME -ap-num 1 -baseaddr $ctibase + target create $_TARGETNAME cortex_r4 -dap $::_DAPNAME \ + -ap-num 1 -dbgbase $dbgbase -defer-examine +} + +proc setup_cm33 {dbgbase ctibase} { + set _TARGETNAME $::_CHIPNAME.m33 + set _CTINAME $_TARGETNAME.cti + cti create $_CTINAME -dap $::_DAPNAME -ap-num 2 -baseaddr $ctibase + target create $_TARGETNAME cortex_m -dap $::_DAPNAME \ + -ap-num 2 -dbgbase $dbgbase -defer-examine +} + +# Organize target list based on the boot core +if { $_boot_core == "CA57" } { + setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 1 + setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 0 + setup_cr7 $CR7_DBGBASE $CR7_CTIBASE +} elseif { $_boot_core == "CA53" } { + setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 1 + setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 0 + setup_cr7 $CR7_DBGBASE $CR7_CTIBASE +} elseif { $_boot_core == "CA55" } { + setup_a5x a55 $CA55_DBGBASE $CA55_CTIBASE $_num_ca55 1 + setup_cm33 $CM33_DBGBASE $CM33_CTIBASE +} +echo "SMP targets:$smp_targets" +eval "target smp $smp_targets" + +if { $_soc == "G2L"} { + target create $_CHIPNAME.axi_ap mem_ap -dap $_DAPNAME -ap-num 1 +} + +proc init_reset {mode} { + # Assert both resets: equivalent to a power-on reset + adapter assert trst assert srst + + # Deassert TRST to begin TAP communication + adapter deassert trst assert srst + + # TAP should now be responsive, validate the scan-chain + jtag arp_init +} diff --git a/tcl/target/rp2040-core0.cfg b/tcl/target/rp2040-core0.cfg index e427083..8c3533b 100644 --- a/tcl/target/rp2040-core0.cfg +++ b/tcl/target/rp2040-core0.cfg @@ -35,4 +35,3 @@ flash bank $_FLASHNAME rp2040_flash $_FLASHBASE $_FLASHSIZE 1 32 $_TARGETNAME # srst does not exist; use SYSRESETREQ to perform a soft reset cortex_m reset_config sysresetreq - diff --git a/tcl/target/snps_em_sk_fpga.cfg b/tcl/target/snps_em_sk_fpga.cfg index 2f7fecb..d09561f 100644 --- a/tcl/target/snps_em_sk_fpga.cfg +++ b/tcl/target/snps_em_sk_fpga.cfg @@ -20,7 +20,7 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -expected-id 0x200444b1 \ -expected-id 0x200044b1 set _coreid 0 -set _dbgbase [expr 0x00000000 | ($_coreid << 13)] +set _dbgbase [expr {0x00000000 | ($_coreid << 13)}] target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME \ -coreid 0 -dbgbase $_dbgbase -endian little diff --git a/tcl/target/snps_hsdk.cfg b/tcl/target/snps_hsdk.cfg index 634e07a..372b406 100644 --- a/tcl/target/snps_hsdk.cfg +++ b/tcl/target/snps_hsdk.cfg @@ -13,7 +13,7 @@ source [find cpu/arc/hs.tcl] set _coreid 0 -set _dbgbase [expr ($_coreid << 13)] +set _dbgbase [expr {$_coreid << 13}] # CHIPNAME will be used to choose core family (600, 700 or EM). As far as # OpenOCD is concerned EM and HS are identical. @@ -30,8 +30,8 @@ $_TARGETNAME configure -coreid $_coreid $_TARGETNAME configure -dbgbase $_dbgbase # Flush L2$. $_TARGETNAME configure -event reset-assert "arc_hs_reset $_TARGETNAME" -set _coreid [expr $_coreid + 1] -set _dbgbase [expr ($_coreid << 13)] +set _coreid [expr {$_coreid + 1}] +set _dbgbase [expr {$_coreid << 13}] arc_hs_init_regs @@ -46,8 +46,8 @@ target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME $_TARGETNAME configure -coreid $_coreid $_TARGETNAME configure -dbgbase $_dbgbase $_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME" -set _coreid [expr $_coreid + 1] -set _dbgbase [expr ($_coreid << 13)] +set _coreid [expr {$_coreid + 1}] +set _dbgbase [expr {$_coreid << 13}] arc_hs_init_regs @@ -62,8 +62,8 @@ target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME $_TARGETNAME configure -coreid $_coreid $_TARGETNAME configure -dbgbase $_dbgbase $_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME" -set _coreid [expr $_coreid + 1] -set _dbgbase [expr ($_coreid << 13)] +set _coreid [expr {$_coreid + 1}] +set _dbgbase [expr {$_coreid << 13}] arc_hs_init_regs @@ -78,8 +78,8 @@ target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME $_TARGETNAME configure -coreid $_coreid $_TARGETNAME configure -dbgbase $_dbgbase $_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME" -set _coreid [expr $_coreid + 1] -set _dbgbase [expr 0x00000000 | ($_coreid << 13)] +set _coreid [expr {$_coreid + 1}] +set _dbgbase [expr {0x00000000 | ($_coreid << 13)}] arc_hs_init_regs # Enable L2 cache support for core 1. diff --git a/tcl/target/stellaris.cfg b/tcl/target/stellaris.cfg index 3cab4d1..4865e29 100644 --- a/tcl/target/stellaris.cfg +++ b/tcl/target/stellaris.cfg @@ -83,7 +83,7 @@ proc reset_peripherals {family} { mmw $SYSCTL_RCC2 $SYSCTL_RCC2_BYPASS2 0 # RCC and RCC2 to their reset values - mww $SYSCTL_RCC [expr (0x078e3ad0 | ([mrw $SYSCTL_RCC] & $SYSCTL_RCC_MOSCDIS))] + mww $SYSCTL_RCC [expr {0x078e3ad0 | ([mrw $SYSCTL_RCC] & $SYSCTL_RCC_MOSCDIS)}] mww $SYSCTL_RCC2 0x07806810 mww $SYSCTL_RCC 0x078e3ad1 @@ -121,8 +121,8 @@ proc reset_peripherals {family} { mww $SYSCTL_MISC 0xffffffff # Wait for any pending flash operations to complete - while {[expr [mrw $FLASH_FMC] & 0xffff] != 0} { sleep 1 } - while {[expr [mrw $FLASH_FMC2] & 0xffff] != 0} { sleep 1 } + while {[expr {[mrw $FLASH_FMC] & 0xffff}] != 0} { sleep 1 } + while {[expr {[mrw $FLASH_FMC2] & 0xffff}] != 0} { sleep 1 } # Reset the flash controller registers mww $FLASH_FMA 0 @@ -152,7 +152,7 @@ $_TARGETNAME configure -event reset-start { if {$_DEVICECLASS != 0xff} { set device_class $_DEVICECLASS } else { - set device_class [expr (([mrw 0x400fe000] >> 16) & 0xff)] + set device_class [expr {([mrw 0x400fe000] >> 16) & 0xff}] } if {$device_class == 0 || $device_class == 1 || diff --git a/tcl/target/stm32f4x.cfg b/tcl/target/stm32f4x.cfg index e94837f..2228de7 100644 --- a/tcl/target/stm32f4x.cfg +++ b/tcl/target/stm32f4x.cfg @@ -38,7 +38,7 @@ if { [info exists CPUTAPID] } { swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu -tpiu create $_CHIPNAME.tpiu -dap stm32f4x.dap -ap-num 0 -baseaddr 0xE0040000 +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 if {[using_jtag]} { jtag newtap $_CHIPNAME bs -irlen 5 diff --git a/tcl/target/stm32h7x.cfg b/tcl/target/stm32h7x.cfg index 26d0d93..877976c 100644 --- a/tcl/target/stm32h7x.cfg +++ b/tcl/target/stm32h7x.cfg @@ -208,7 +208,7 @@ proc stm32h7x_get_chipname {} { if {$sep == -1} { return $t } - return [string range $t 0 [expr $sep - 1]] + return [string range $t 0 [expr {$sep - 1}]] } if {[set $_CHIPNAME.DUAL_CORE]} { @@ -240,7 +240,7 @@ proc stm32h7x_mrw {used_target reg} { # like mmw, but with target selection proc stm32h7x_mmw {used_target reg setbits clearbits} { set old [stm32h7x_mrw $used_target $reg] - set new [expr ($old & ~$clearbits) | $setbits] + set new [expr {($old & ~$clearbits) | $setbits}] $used_target mww $reg $new } @@ -251,10 +251,10 @@ proc stm32h7x_dbgmcu_mmw {reg_offset setbits clearbits} { if {![using_hla]} { set _CHIPNAME [stm32h7x_get_chipname] set used_target $_CHIPNAME.ap2 - set reg_addr [expr 0xE00E1000 + $reg_offset] + set reg_addr [expr {0xE00E1000 + $reg_offset}] } { set used_target [target current] - set reg_addr [expr 0x5C001000 + $reg_offset] + set reg_addr [expr {0x5C001000 + $reg_offset}] } stm32h7x_mmw $used_target $reg_addr $setbits $clearbits diff --git a/tcl/target/stm32mp15x.cfg b/tcl/target/stm32mp15x.cfg index 1b2ae7d..e50ef9c 100644 --- a/tcl/target/stm32mp15x.cfg +++ b/tcl/target/stm32mp15x.cfg @@ -107,7 +107,7 @@ proc toggle_cpu0_dbg_claim0 {} { proc detect_cpu1 {} { $::_CHIPNAME.ap1 mem2array cpu1_prsr 32 0xE00D2314 1 - set dual_core [expr $cpu1_prsr(0) & 1] + set dual_core [expr {$cpu1_prsr(0) & 1}] if {! $dual_core} {$::_CHIPNAME.cpu1 configure -defer-examine} } diff --git a/tcl/target/ti_dm355.cfg b/tcl/target/ti_dm355.cfg index 91c0087..19fb0b6 100644 --- a/tcl/target/ti_dm355.cfg +++ b/tcl/target/ti_dm355.cfg @@ -90,7 +90,7 @@ target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME # NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel, # and that the work area is used only with a kernel mmu context ... $_TARGETNAME configure \ - -work-area-virt [expr 0xfffe0000 + 0x4000] \ + -work-area-virt [expr {0xfffe0000 + 0x4000}] \ -work-area-phys [dict get $dm355 sram1] \ -work-area-size 0x4000 \ -work-area-backup 0 diff --git a/tcl/target/ti_dm365.cfg b/tcl/target/ti_dm365.cfg index 8b52746..f71a77a 100644 --- a/tcl/target/ti_dm365.cfg +++ b/tcl/target/ti_dm365.cfg @@ -82,7 +82,7 @@ target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME # NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel, # and that the work area is used only with a kernel mmu context ... $_TARGETNAME configure \ - -work-area-virt [expr 0xfffe0000 + 0x4000] \ + -work-area-virt [expr {0xfffe0000 + 0x4000}] \ -work-area-phys [dict get $dm365 sram1] \ -work-area-size 0x4000 \ -work-area-backup 0 diff --git a/tcl/target/u8500.cfg b/tcl/target/u8500.cfg index 36e0db7..5aee135 100644 --- a/tcl/target/u8500.cfg +++ b/tcl/target/u8500.cfg @@ -4,13 +4,13 @@ proc mmu_off {} { set cp [arm mrc 15 0 1 0 0] - set cp [expr ($cp & ~1)] + set cp [expr {$cp & ~1}] arm mcr 15 0 1 0 0 $cp } proc mmu_on {} { set cp [arm mrc 15 0 1 0 0] - set cp [expr ($cp | 1)] + set cp [expr {$cp | 1}] arm mcr 15 0 1 0 0 $cp } @@ -18,12 +18,12 @@ proc ocd_gdb_restart {target_id} { global _TARGETNAME_1 global _SMP targets $_TARGETNAME_1 - if { [expr ($_SMP == 1)] } { + if { $_SMP == 1 } { cortex_a smp off } rst_run halt - if { [expr ($_SMP == 1)]} { + if { $_SMP == 1 } { cortex_a smp on } } @@ -52,9 +52,9 @@ proc pwrsts { } { irscan $_CHIPNAME.jrc 0x3a drscan $_CHIPNAME.jrc 4 0 set pwrsts [drscan $_CHIPNAME.jrc 16 0] - echo "pwrsts ="$pwrsts - set a9 [expr (0x$pwrsts & 0xc)] - set ape [expr (0x$pwrsts & 0x3)] + echo "pwrsts ="$pwrsts + set a9 [expr "0x$pwrsts & 0xc"] + set ape [expr "0x$pwrsts & 0x3"] if {[string equal "0" $ape]} { echo "ape off" } else { @@ -81,12 +81,12 @@ proc poll_pwrsts { } { irscan $_CHIPNAME.jrc 0x3a drscan $_CHIPNAME.jrc 4 0 set pwrsts [drscan $_CHIPNAME.jrc 16 0] - set pwrsts [expr (0x$pwrsts & 0xc)] + set pwrsts [expr "0x$pwrsts & 0xc"] while {[string equal "4" $pwrsts] && $i<20} { irscan $_CHIPNAME.jrc 0x3a drscan $_CHIPNAME.jrc 4 0; set pwrsts [drscan $_CHIPNAME.jrc 16 0] - set pwrsts [expr (0x$pwrsts & 0xc)] + set pwrsts [expr "0x$pwrsts & 0xc"] if {![string equal "4" $pwrsts]} { set result 1 } else { @@ -239,7 +239,7 @@ proc secsts1 { } { drscan $_CHIPNAME.jrc 4 4 set secsts1 [drscan $_CHIPNAME.jrc 16 0] echo "secsts1 ="$secsts1 - set secsts1 [expr (0x$secsts1 & 0x4)] + set secsts1 [expr "0x$secsts1 & 0x4"] if {![string equal "4" $secsts1]} { echo "APE target secured" } else { @@ -254,7 +254,7 @@ proc att { } { drscan $_CHIPNAME.jrc 4 4 set secsts1 [drscan $_CHIPNAME.jrc 16 0] echo "secsts1 ="$secsts1 - set secsts1 [expr (0x$secsts1 & 0x4)] + set secsts1 [expr "0x$secsts1 & 0x4"] if {[string equal "4" $secsts1]} { if {[poll_pwrsts]==1} { enable_apetap @@ -291,13 +291,13 @@ proc rst_run { } { drscan $_CHIPNAME.jrc 4 4 set secsts1 [drscan $_CHIPNAME.jrc 16 0] echo "secsts1 ="$secsts1 - set secsts1 [expr (0x$secsts1 & 0x4)] + set secsts1 [expr "0x$secsts1 & 0x4"] while {![string equal "4" $secsts1]} { irscan u8500.jrc 0x3a drscan u8500.jrc 4 4 set secsts1 [drscan $_CHIPNAME.jrc 16 0] echo "secsts1 ="$secsts1 - set secsts1 [expr (0x$secsts1 & 0x4)] + set secsts1 [expr "0x$secsts1 & 0x4"] } echo "ape debugable" enable_apetap diff --git a/tcl/target/xilinx_zynqmp.cfg b/tcl/target/xilinx_zynqmp.cfg index b21603f..e66289a 100644 --- a/tcl/target/xilinx_zynqmp.cfg +++ b/tcl/target/xilinx_zynqmp.cfg @@ -92,6 +92,8 @@ for { set _core 0 } { $_core < $_cores } { incr _core } { eval $_command } +target create uscale.axi mem_ap -dap uscale.dap -ap-num 0 + eval $_smp_command targets $_TARGETNAME.0 -- cgit v1.1