From 3d736e0488bc498358e3d49d7ce728b17955c8fe Mon Sep 17 00:00:00 2001
From: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Date: Wed, 25 Mar 2020 16:33:30 +0100
Subject: flash/stm32l4x: STM32L55/L56xx basic support (non-secure mode)

STM32L5 have 512 Kbytes of Flash memory with dual bank architecture.
STM32L5 flash is quite similar to L4 flash, mainly register names
and offsets and some bits are changed.
NON-SECURE flash is located at 0x8000000 like L4 devices, so no
big change is needed (secure flash will be subject of another change).

Note: flash driver name is set stm32l5x, in order to extend the commands
with specific L5 commands (to manage TZEN for example ...)

Note: this works only when TZEN=0

Change-Id: Ie758abb4aa19a3f29eeb0702d7dcb43992e4c639
Signed-off-by: Michael Jung <mijung@gmx.net>
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5510
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
---
 tcl/target/stm32l5x.cfg | 130 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 130 insertions(+)
 create mode 100644 tcl/target/stm32l5x.cfg

(limited to 'tcl/target/stm32l5x.cfg')

diff --git a/tcl/target/stm32l5x.cfg b/tcl/target/stm32l5x.cfg
new file mode 100644
index 0000000..bf56360
--- /dev/null
+++ b/tcl/target/stm32l5x.cfg
@@ -0,0 +1,130 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32l5x family
+
+#
+# stm32l5 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32l5x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 64kB
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x10000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	if { [using_jtag] } {
+		# See STM Document RM0438
+		# RM0438 Rev5, Section 52.2.8 JTAG debug port - Table 425. JTAG-DP data registers
+		# Corresponds to Cortex®-M33 JTAG debug port ID code
+		set _CPUTAPID 0x0ba04477
+	} {
+		# SWD IDCODE (single drop, arm)
+		set _CPUTAPID 0x0be12477
+	}
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+	jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+# use non-secure RAM by default
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# declare non-secure flash
+flash bank $_CHIPNAME.flash_ns stm32l4x 0 0 0 0 $_TARGETNAME
+
+# Common knowledges tells JTAG speed should be <= F_CPU/6.
+# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
+# the safe side.
+#
+# Note that there is a pretty wide band where things are
+# more or less stable, see http://openocd.zylin.com/#/c/3366/
+adapter speed 500
+
+adapter srst delay 100
+if {[using_jtag]} {
+	jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+	# if srst is not fitted use SYSRESETREQ to
+	# perform a soft reset
+	cortex_m reset_config sysresetreq
+}
+
+proc clock_config_110_mhz {} {
+	# MCU clock is MSI (4MHz) after reset, set MCU freq at 110 MHz with PLL
+	# RCC_APB1ENR1 = PWREN
+	mww 0x40021058 0x10000000
+	# delay for register clock enable (read back reg)
+	mrw 0x40021058
+	# PWR_CR1 : VOS Range 0
+	mww 0x40007000 0
+	# while (PWR_SR2 & VOSF)
+	while {([mrw 0x40007014] & 0x0400)} {}
+	# FLASH_ACR : 5 WS for 110 MHz HCLK
+	mww 0x40022000 0x00000005
+	# RCC_PLLCFGR = PLLP=PLLQ=0, PLLR=00=2, PLLREN=1, PLLN=55, PLLM=0000=1, PLLSRC=MSI 4MHz
+	# fVCO = 4 x 55 /1 = 220
+	# SYSCLOCK = fVCO/PLLR = 220/2 = 110 MHz
+	mww 0x4002100C 0x01003711
+	# RCC_CR |= PLLON
+	mmw 0x40021000 0x01000000 0
+	# while !(RCC_CR & PLLRDY)
+	while {!([mrw 0x40021000] & 0x02000000)} {}
+	# RCC_CFGR |= SW_PLL
+	mmw 0x40021008 0x00000003 0
+	# while ((RCC_CFGR & SWS) != PLL)
+	while {([mrw 0x40021008] & 0x0C) != 0x0C} {}
+}
+
+$_TARGETNAME configure -event reset-init {
+	clock_config_110_mhz
+	# Boost JTAG frequency
+	adapter speed 4000
+}
+
+$_TARGETNAME configure -event reset-start {
+	# Reset clock is MSI (4 MHz)
+	adapter speed 480
+}
+
+$_TARGETNAME configure -event examine-end {
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
+	mmw 0xE0044004 0x00000006 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+	mmw 0xE0044008 0x00001800 0
+}
+
+$_TARGETNAME configure -event trace-config {
+	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+	# change this value accordingly to configure trace pins
+	# assignment
+	mmw 0xE0044004 0x00000020 0
+}
-- 
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