From 24b656bff5889350b0c95d791d47e479d9fbd7f9 Mon Sep 17 00:00:00 2001 From: Jacek Wuwer Date: Mon, 29 May 2023 19:00:27 +0200 Subject: jtag/vdebug: adding xtensa config This change adds the extensa sample target and board configurations. it removes the obsoleted vd_xtensa_jtag.cfg from targets. Change-Id: I9d4d25abde46c0b15e5211a973012447872cb405 Signed-off-by: Jacek Wuwer Reviewed-on: https://review.openocd.org/c/openocd/+/7723 Reviewed-by: Antonio Borneo Tested-by: jenkins --- tcl/board/vd_xt8_jtag.cfg | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 tcl/board/vd_xt8_jtag.cfg (limited to 'tcl/board') diff --git a/tcl/board/vd_xt8_jtag.cfg b/tcl/board/vd_xt8_jtag.cfg new file mode 100644 index 0000000..867b9e7 --- /dev/null +++ b/tcl/board/vd_xt8_jtag.cfg @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Cadence virtual debug interface +# Xtensa xt8 through JTAG + +source [find interface/vdebug.cfg] + +set CHIPNAME xt8 +set CPUTAPID 0x120034e5 + +# vdebug select transport +transport select jtag + +# JTAG reset config, frequency and reset delay +reset_config trst_and_srst +adapter speed 50000 +adapter srst delay 5 + +# BFM hierarchical path and input clk period +vdebug bfm_path Testbench.u_vd_jtag_bfm 10ns + +# DMA Memories to access backdoor, the values come from generated xtensa-core-xt8.cfg +#vdebug mem_path Testbench.Xtsubsystem.Core0.iram0.iram0.mem.dataArray 0x40000000 0x100000 +#vdebug mem_path Testbench.Xtsubsystem.Core0.dram0.dram0.mem.dataArray 0x3ff00000 0x40000 + +# Create Xtensa target first +source [find target/xtensa.cfg] +# Generate [xtensa-core-XXX.cfg] via "xt-gdb --dump-oocd-config" +source [find target/xtensa-core-xt8.cfg] -- cgit v1.1