From 2e6904eef5e81e71453168ed8c6f649e3a5c0f6c Mon Sep 17 00:00:00 2001 From: Lucas Date: Sun, 17 May 2020 16:42:39 +0100 Subject: aarch64: Add support for debugging in HYP mode on ARMv8-A cores MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When debugging an ARMv8-A/AArch32 target running HYP mode, OpenOCD would throw the following error to GDB on most operations (step, set breakpoint): cannot read system control register in this mode The mode in question is 0x1A, a privilege level 2 mode available on cores that have the virtualization extensions (such as the Raspi 3). Note: this mode is only used when running in AArch32 compatibility mode. Signed-off-by: Lucas Jenss Signed-off-by: Tarek BOCHKATI Change-Id: Ia8673ff34c5b3eed60e24d8da57c3ca8197a60c2 Reviewed-on: http://openocd.zylin.com/5255 Tested-by: jenkins Reviewed-by: Lucas Jenß Reviewed-by: Antonio Borneo --- src/target/armv8.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/target/armv8.c') diff --git a/src/target/armv8.c b/src/target/armv8.c index 61f11f2..0c85086 100644 --- a/src/target/armv8.c +++ b/src/target/armv8.c @@ -74,6 +74,10 @@ static const struct { .psr = ARM_MODE_ABT, }, { + .name = "HYP", + .psr = ARM_MODE_HYP, + }, + { .name = "SYS", .psr = ARM_MODE_SYS, }, -- cgit v1.1