From 6fb9f2e3ee05d8ff6241e6d61f7de0e71afeb45c Mon Sep 17 00:00:00 2001 From: Matthias Welwarsky Date: Wed, 15 Feb 2017 14:57:21 +0100 Subject: armv8: factor out generic bit set/clr for debug registers introduce armv8_set_dbgreg_bits() function to make register bit-field modifications easier to read. Change-Id: I6b06f66262587fd301d848c9e0645e8327653de7 Signed-off-by: Matthias Welwarsky Reviewed-on: http://openocd.zylin.com/3989 Tested-by: jenkins Reviewed-by: Paul Fertser --- src/target/aarch64.c | 18 +----------------- 1 file changed, 1 insertion(+), 17 deletions(-) (limited to 'src/target/aarch64.c') diff --git a/src/target/aarch64.c b/src/target/aarch64.c index 5dd6d7a..65a5278 100644 --- a/src/target/aarch64.c +++ b/src/target/aarch64.c @@ -238,23 +238,7 @@ static int aarch64_dpm_setup(struct aarch64_common *a8, uint64_t debug) static int aarch64_set_dscr_bits(struct target *target, unsigned long bit_mask, unsigned long value) { struct armv8_common *armv8 = target_to_armv8(target); - uint32_t dscr; - - /* Read DSCR */ - int retval = mem_ap_read_atomic_u32(armv8->debug_ap, - armv8->debug_base + CPUV8_DBG_DSCR, &dscr); - if (ERROR_OK != retval) - return retval; - - /* clear bitfield */ - dscr &= ~bit_mask; - /* put new value */ - dscr |= value & bit_mask; - - /* write new DSCR */ - retval = mem_ap_write_atomic_u32(armv8->debug_ap, - armv8->debug_base + CPUV8_DBG_DSCR, dscr); - return retval; + return armv8_set_dbgreg_bits(armv8, CPUV8_DBG_DSCR, bit_mask, value); } static struct target *get_aarch64(struct target *target, int32_t coreid) -- cgit v1.1