From 2839a873a3e93c8f744352fc1671c2db6297937b Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Mon, 28 Aug 2023 12:11:48 +0200 Subject: doc/style: clarify default case for enumerators Enumerator's case were not specified in the coding style. Add enumerators together with macros for upper-case preference. While there, add the word CamelCase beside the less common, but already used, MixedCaps. This could help linking this chapter to the output of checkpatch script. Change-Id: I6d4af06cc6f4bc46f525e99e9a74ecc167606c49 Signed-off-by: Antonio Borneo Reviewed-on: https://review.openocd.org/c/openocd/+/7875 Reviewed-by: Tomas Vanek Tested-by: jenkins --- doc/manual/style.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'doc') diff --git a/doc/manual/style.txt b/doc/manual/style.txt index 58f3980..1d3ec67 100644 --- a/doc/manual/style.txt +++ b/doc/manual/style.txt @@ -111,8 +111,8 @@ Finally, try to avoid lines of code that are longer than 72-80 columns: @section stylenames Naming Rules - most identifiers must use lower-case letters (and digits) only. - - macros must use upper-case letters (and digits) only. - - OpenOCD identifiers should NEVER use @c MixedCaps. + - macros and enumerators must use upper-case letters (and digits) only. + - OpenOCD identifiers should NEVER use @c MixedCaps, aka @c CamelCase. - @c typedef names must end with the '_t' suffix. - This should be reserved for types that should be passed by value. - Do @b not mix the typedef keyword with @c struct. -- cgit v1.1 From 62f76b2169302b9500deea737a017168271824ac Mon Sep 17 00:00:00 2001 From: Luca Hung Date: Mon, 31 Jul 2023 15:08:18 +0800 Subject: flash/nor: add support for Nuvoton NPCX4/K3 series flash Added NPCX flash driver to support the Nuvoton NPCX4/K3 series microcontrollers. Add config file for these series. Change-Id: I0b6e128fa51146b561f422e23a98260594b1f138 Signed-off-by: Luca Hung Signed-off-by: Mulin CHao Reviewed-on: https://review.openocd.org/c/openocd/+/7794 Tested-by: jenkins Reviewed-by: Tomas Vanek Reviewed-by: Antonio Borneo --- doc/openocd.texi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'doc') diff --git a/doc/openocd.texi b/doc/openocd.texi index d07188c..f6f7a0c 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -7193,10 +7193,16 @@ Show information about flash driver. All versions of the NPCX microcontroller families from Nuvoton include internal flash. The NPCX flash driver supports the NPCX family of devices. The driver automatically recognizes the specific version's flash parameters and -autoconfigures itself. The flash bank starts at address 0x64000000. +autoconfigures itself. The flash bank starts at address 0x64000000. An optional additional +parameter sets the FIU version for the bank, with the default FIU is @var{npcx.fiu}. @example + +flash bank $_FLASHNAME npcx 0x64000000 0 0 0 $_TARGETNAME npcx_v2.fiu + +# FIU defaults to npcx.fiu flash bank $_FLASHNAME npcx 0x64000000 0 0 0 $_TARGETNAME + @end example @end deffn -- cgit v1.1 From fe5ed48f40e4f1b36d74900d0d9b410affea6bdb Mon Sep 17 00:00:00 2001 From: Daniel Anselmi Date: Fri, 24 Feb 2023 15:57:30 +0100 Subject: jtagspi/pld: add interface to get support from pld drivers Jtagspi is using a proxy bitstream to "connect" JTAG to the SPI pins. This is not possible with all FPGA vendors/families. In this cases a dedicated procedure is needed to establish such a connection. This patch adds a jtagspi-mode for these cases. It also adds the needed interfaces to jtagspi and the pld-driver so the driver can select the mode and provide the necessary procedures. For the cases where a proxy bitstream is needed, the pld driver will select the mode and provide instruction code needed in this case. Change-Id: I9563f26739589157b39a3664a73d91152cd13f77 Signed-off-by: Daniel Anselmi Reviewed-on: https://review.openocd.org/c/openocd/+/7822 Tested-by: jenkins Reviewed-by: Antonio Borneo --- doc/openocd.texi | 56 +++++++++++++++++++++++++++++++++++++++++++------------- 1 file changed, 43 insertions(+), 13 deletions(-) (limited to 'doc') diff --git a/doc/openocd.texi b/doc/openocd.texi index f6f7a0c..7ad48c8 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -5900,24 +5900,42 @@ flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME @c "cfi part_id" disabled @end deffn +@anchor{jtagspi} @deffn {Flash Driver} {jtagspi} @cindex Generic JTAG2SPI driver @cindex SPI @cindex jtagspi @cindex bscan_spi Several FPGAs and CPLDs can retrieve their configuration (bitstream) from a -SPI flash connected to them. To access this flash from the host, the device -is first programmed with a special proxy bitstream that -exposes the SPI flash on the device's JTAG interface. The flash can then be -accessed through JTAG. +SPI flash connected to them. To access this flash from the host, some FPGA +device provides dedicated JTAG instructions, while other FPGA devices should +be programmed with a special proxy bitstream that exposes the SPI flash on +the device's JTAG interface. The flash can then be accessed through JTAG. -Since signaling between JTAG and SPI is compatible, all that is required for +Since signalling between JTAG and SPI is compatible, all that is required for a proxy bitstream is to connect TDI-MOSI, TDO-MISO, TCK-CLK and activate -the flash chip select when the JTAG state machine is in SHIFT-DR. Such -a bitstream for several Xilinx FPGAs can be found in +the flash chip select when the JTAG state machine is in SHIFT-DR. + +Such a bitstream for several Xilinx FPGAs can be found in @file{contrib/loaders/flash/fpga/xilinx_bscan_spi.py}. It requires @uref{https://github.com/m-labs/migen, migen} and a Xilinx toolchain to build. +This mechanism with a proxy bitstream can also be used for FPGAs from Intel and +Efinix. FPGAs from Lattice and Cologne Chip have dedicated JTAG instructions +and procedure to connect the JTAG to the SPI signals and don't need a proxy +bitstream. Support for these devices with dedicated procedure is provided by +the pld drivers. For convenience the PLD drivers will provide the USERx code +for FPGAs with a proxy bitstream. Currently the following PLD drivers are able +to support jtagspi: +@itemize +@item Efinix: proxy-bitstream +@item Gatemate: dedicated procedure +@item Intel/Altera: proxy-bitstream +@item Lattice: dedicated procedure supporting ECP2, ECP3, ECP5, Certus and Certus Pro devices +@item AMD/Xilinx: proxy-bitstream +@end itemize + + This flash bank driver requires a target on a JTAG tap and will access that tap directly. Since no support from the target is needed, the target can be a "testee" dummy. Since the target does not expose the flash memory @@ -5935,14 +5953,25 @@ command, see below. @item @var{ir} ... is loaded into the JTAG IR to map the flash as the JTAG DR. For the bitstreams generated from @file{xilinx_bscan_spi.py} this is the @var{USER1} instruction. -@end itemize +@example +target create $_TARGETNAME testee -chain-position $_CHIPNAME.tap +set _USER1_INSTR_CODE 0x02 +flash bank $_FLASHNAME jtagspi 0x0 0 0 0 \ + $_TARGETNAME $_USER1_INSTR_CODE +@end example + +@item The option @option{-pld} @var{name} is used to have support from the +PLD driver of pld device @var{name}. The name is the name of the pld device +given during creation of the pld device. +Pld device names are shown by the @command{pld devices} command. @example -target create $_TARGETNAME testee -chain-position $_CHIPNAME.fpga -set _XILINX_USER1 0x02 -flash bank $_FLASHNAME spi 0x0 0 0 0 \ - $_TARGETNAME $_XILINX_USER1 +target create $_TARGETNAME testee -chain-position $_CHIPNAME.tap +set _JTAGSPI_CHAIN_ID $_CHIPNAME.pld +flash bank $_FLASHNAME jtagspi 0x0 0 0 0 \ + $_TARGETNAME -pld $_JTAGSPI_CHAIN_ID @end example +@end itemize @deffn Command {jtagspi set} bank_id name total_size page_size read_cmd unused pprg_cmd mass_erase_cmd sector_size sector_erase_cmd Sets flash parameters: @var{name} human readable string, @var{total_size} @@ -8668,7 +8697,8 @@ Accordingly, both are called PLDs here. As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND), OpenOCD maintains a list of PLDs available for use in various commands. -Also, each such PLD requires a driver. +Also, each such PLD requires a driver. PLD drivers may also be needed to program +SPI flash connected to the FPGA to store the bitstream (@xref{jtagspi} for details). They are referenced by the name which was given when the pld was created or the number shown by the @command{pld devices} command. -- cgit v1.1 From eb22a37b42a7944694243b690bfbd736e1ef52e8 Mon Sep 17 00:00:00 2001 From: Daniel Anselmi Date: Sat, 17 Dec 2022 13:11:30 +0100 Subject: pld: harmonize refresh commands add refresh command for lattice devices rename gowin reprogram to refresh rename virtex2 program to refresh Change-Id: I9da83a614b96da3e947ac4608b0a291b1d126914 Signed-off-by: Daniel Anselmi Reviewed-on: https://review.openocd.org/c/openocd/+/7839 Tested-by: jenkins Reviewed-by: Antonio Borneo --- doc/openocd.texi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'doc') diff --git a/doc/openocd.texi b/doc/openocd.texi index 7ad48c8..2d59238 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -8764,8 +8764,8 @@ Change values for boundary scan instructions selecting the registers USER1 to US Description of the arguments can be found at command @command{virtex2 set_instr_codes}. @end deffn -@deffn {Command} {virtex2 program} pld_name -Load the bitstream from external memory for FPGA @var{pld_name}. A.k.a. refresh. +@deffn {Command} {virtex2 refresh} pld_name +Load the bitstream from external memory for FPGA @var{pld_name}. A.k.a. program. @end deffn @end deffn @@ -8796,6 +8796,10 @@ for FPGA @var{pld_name} with value @var{val}. Set the length of the register for the preload. This is needed when the JTAG ID of the device is not known by openocd (newer NX devices). The load command for the FPGA @var{pld_name} will use a length for the preload of @var{length}. @end deffn + +@deffn {Command} {lattice refresh} pld_name +Load the bitstream from external memory for FPGA @var{pld_name}. A.k.a program. +@end deffn @end deffn @@ -8850,9 +8854,9 @@ Reads and displays the user register for FPGA @var{pld_name}. @end deffn -@deffn {Command} {gowin reload} pld_name +@deffn {Command} {gowin refresh} pld_name Load the bitstream from external memory for -FPGA @var{pld_name}. A.k.a. refresh. +FPGA @var{pld_name}. A.k.a. reload. @end deffn @end deffn -- cgit v1.1