From 019bf5f83c79353392471529f7cb961c5c603bfd Mon Sep 17 00:00:00 2001 From: Walter Ji Date: Fri, 17 Nov 2023 15:13:55 +0800 Subject: target/mips32: add mips ejtag command Add mips32 ejtag_reg command for inspecting ejtag status. Add description for mips32 ejtag_reg command. Change-Id: Icd173d3397d568b0c004a8cc3f45518d7b48ce43 Signed-off-by: Walter Ji Reviewed-on: https://review.openocd.org/c/openocd/+/7906 Reviewed-by: Oleksij Rempel Reviewed-by: Antonio Borneo Tested-by: jenkins --- doc/openocd.texi | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'doc/openocd.texi') diff --git a/doc/openocd.texi b/doc/openocd.texi index a2af451..e482c43 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -11037,10 +11037,17 @@ For common MIPS Coprocessor 0 registers, you can find the definitions of them on MIPS Privileged Resource Architecture Documents(MIPS Document MD00090). For core specific cp0 registers, you can find the definitions of them on Core -Specific Software User's Manual, for example, MIPS M5150 Software User Manual +Specific Software User's Manual(SUM), for example, MIPS M5150 Software User Manual (MD00980). @end deffn +@deffn {Command} {mips32 ejtag_reg} +Reads EJTAG Registers for inspection. + +EJTAG Register Specification could be found in MIPS Document MD00047F, for +core specific EJTAG Register definition, please check Core Specific SUM manual. +@end deffn + @section RISC-V Architecture @uref{http://riscv.org/, RISC-V} is a free and open ISA. OpenOCD supports JTAG -- cgit v1.1