From 0944e12232c165cef5a8cbc6d5921e11803c832f Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Sun, 16 May 2021 13:40:55 +0200 Subject: riscv: drop unused variable The array newly_halted[] is assigned but its value is never used. Drop it! Change-Id: I678812a31c45a3ec03716e3eee6a30b8e8947926 Signed-off-by: Antonio Borneo --- src/target/riscv/riscv.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index a8838d9..d350e01 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -2110,7 +2110,6 @@ int riscv_openocd_poll(struct target *target) if (target->smp) { unsigned halts_discovered = 0; - bool newly_halted[RISCV_MAX_HARTS] = {0}; unsigned should_remain_halted = 0; unsigned should_resume = 0; unsigned i = 0; @@ -2118,7 +2117,6 @@ int riscv_openocd_poll(struct target *target) list = list->next, i++) { struct target *t = list->target; riscv_info_t *r = riscv_info(t); - assert(i < DIM(newly_halted)); enum riscv_poll_hart out = riscv_poll_hart(t, r->current_hartid); switch (out) { case RPH_NO_CHANGE: @@ -2129,7 +2127,6 @@ int riscv_openocd_poll(struct target *target) break; case RPH_DISCOVERED_HALTED: halts_discovered++; - newly_halted[i] = true; t->state = TARGET_HALTED; enum riscv_halt_reason halt_reason = riscv_halt_reason(t, r->current_hartid); -- cgit v1.1 From 6f5259db05b262faac84a58bf3d7c3ddff394281 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Sun, 16 May 2021 13:53:10 +0200 Subject: riscv: prefer ARRAY_SIZE() to DIM() OpenOCD already defines the macro ARRAY_SIZE, while riscv code uses a local macro DIM. Prefer using the macro ARRAY_SIZE() instead of DIM(). Not all the riscv code has been upstreamed, yes; this patch only covers the code not upstreamed. Change-Id: Ie3e411280f76bc798f1d51c2574cfec148ee0d0d Signed-off-by: Antonio Borneo --- src/target/riscv/riscv-013.c | 6 +++--- src/target/riscv/riscv.c | 10 +++++----- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 80fe5e5..b6777cb 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -2159,7 +2159,7 @@ static int sample_memory_bus_v1(struct target *target, const unsigned repeat = 5; unsigned enabled_count = 0; - for (unsigned i = 0; i < DIM(config->bucket); i++) { + for (unsigned i = 0; i < ARRAY_SIZE(config->bucket); i++) { if (config->bucket[i].enabled) enabled_count++; } @@ -2176,7 +2176,7 @@ static int sample_memory_bus_v1(struct target *target, unsigned result_bytes = 0; for (unsigned n = 0; n < repeat; n++) { - for (unsigned i = 0; i < DIM(config->bucket); i++) { + for (unsigned i = 0; i < ARRAY_SIZE(config->bucket); i++) { if (config->bucket[i].enabled) { if (!sba_supports_access(target, config->bucket[i].size_bytes)) { LOG_ERROR("Hardware does not support SBA access for %d-byte memory sampling.", @@ -2244,7 +2244,7 @@ static int sample_memory_bus_v1(struct target *target, unsigned read = 0; for (unsigned n = 0; n < repeat; n++) { - for (unsigned i = 0; i < DIM(config->bucket); i++) { + for (unsigned i = 0; i < ARRAY_SIZE(config->bucket); i++) { if (config->bucket[i].enabled) { assert(i < RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE); uint64_t value = 0; diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index d350e01..20f9e2f 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -2076,7 +2076,7 @@ int sample_memory(struct target *target) /* Default slow path. */ while (timeval_ms() - start < TARGET_DEFAULT_POLLING_INTERVAL) { - for (unsigned i = 0; i < DIM(r->sample_config.bucket); i++) { + for (unsigned i = 0; i < ARRAY_SIZE(r->sample_config.bucket); i++) { if (r->sample_config.bucket[i].enabled && r->sample_buf.used + 1 + r->sample_config.bucket[i].size_bytes < r->sample_buf.size) { assert(i < RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE); @@ -2866,7 +2866,7 @@ COMMAND_HANDLER(handle_memory_sample_command) if (CMD_ARGC == 0) { command_print(CMD, "Memory sample configuration for %s:", target_name(target)); - for (unsigned i = 0; i < DIM(r->sample_config.bucket); i++) { + for (unsigned i = 0; i < ARRAY_SIZE(r->sample_config.bucket); i++) { if (r->sample_config.bucket[i].enabled) { command_print(CMD, "bucket %d; address=0x%" TARGET_PRIxADDR "; size=%d", i, r->sample_config.bucket[i].address, @@ -2885,8 +2885,8 @@ COMMAND_HANDLER(handle_memory_sample_command) uint32_t bucket; COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], bucket); - if (bucket > DIM(r->sample_config.bucket)) { - LOG_ERROR("Max bucket number is %d.", (unsigned) DIM(r->sample_config.bucket)); + if (bucket > ARRAY_SIZE(r->sample_config.bucket)) { + LOG_ERROR("Max bucket number is %d.", (unsigned) ARRAY_SIZE(r->sample_config.bucket)); return ERROR_COMMAND_ARGUMENT_INVALID; } @@ -2964,7 +2964,7 @@ COMMAND_HANDLER(handle_dump_sample_buf_command) uint32_t timestamp = buf_get_u32(r->sample_buf.buf + i, 0, 32); i += 4; command_print(CMD, "timestamp after: %u", timestamp); - } else if (command < DIM(r->sample_config.bucket)) { + } else if (command < ARRAY_SIZE(r->sample_config.bucket)) { command_print_sameline(CMD, "0x%" TARGET_PRIxADDR ": ", r->sample_config.bucket[command].address); if (r->sample_config.bucket[command].size_bytes == 4) { -- cgit v1.1 From 9bdd1daec317dfc6e258dc1c9056e1eacc0709a2 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Sun, 16 May 2021 13:57:11 +0200 Subject: riscv: replace macro DIM() with ARRAY_SIZE() OpenOCD already defines the macro ARRAY_SIZE, while riscv code uses a local macro DIM. Prefer using the macro ARRAY_SIZE() instead of DIM(). Not all the riscv code has been upstreamed, yes; this patch only covers the code already upstreamed. Change-Id: I89a58a6d91916d85c53ba5e4091b558271f8d618 Signed-off-by: Antonio Borneo --- src/target/riscv/riscv-011.c | 4 +--- src/target/riscv/riscv-013.c | 4 +--- src/target/riscv/riscv.c | 16 +++++++--------- 3 files changed, 9 insertions(+), 15 deletions(-) diff --git a/src/target/riscv/riscv-011.c b/src/target/riscv/riscv-011.c index c70d5d8..2d69149 100644 --- a/src/target/riscv/riscv-011.c +++ b/src/target/riscv/riscv-011.c @@ -70,8 +70,6 @@ #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1))) #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask))) -#define DIM(x) (sizeof(x)/sizeof(*x)) - /* Constants for legacy SiFive hardware breakpoints. */ #define CSR_BPCONTROL_X (1<<0) #define CSR_BPCONTROL_W (1<<1) @@ -1634,7 +1632,7 @@ static riscv_error_t handle_halt_routine(struct target *target) /* Read S0 from dscratch */ unsigned int csr[] = {CSR_DSCRATCH0, CSR_DPC, CSR_DCSR}; - for (unsigned int i = 0; i < DIM(csr); i++) { + for (unsigned int i = 0; i < ARRAY_SIZE(csr); i++) { scans_add_write32(scans, 0, csrr(S0, csr[i]), true); scans_add_read(scans, SLOT0, false); } diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index b6777cb..cfc040c 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -85,8 +85,6 @@ void read_memory_sba_simple(struct target *target, target_addr_t addr, #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1))) #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask))) -#define DIM(x) (sizeof(x)/sizeof(*x)) - #define CSR_DCSR_CAUSE_SWBP 1 #define CSR_DCSR_CAUSE_TRIGGER 2 #define CSR_DCSR_CAUSE_DEBUGINT 3 @@ -361,7 +359,7 @@ static void decode_dmi(char *text, unsigned address, unsigned data) }; text[0] = 0; - for (unsigned i = 0; i < DIM(description); i++) { + for (unsigned i = 0; i < ARRAY_SIZE(description); i++) { if (description[i].address == address) { uint64_t mask = description[i].mask; unsigned value = get_field(data, mask); diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 20f9e2f..8cfb227 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -24,8 +24,6 @@ #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1))) #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask))) -#define DIM(x) (sizeof(x)/sizeof(*x)) - /* Constants for legacy SiFive hardware breakpoints. */ #define CSR_BPCONTROL_X (1<<0) #define CSR_BPCONTROL_W (1<<1) @@ -185,10 +183,10 @@ struct scan_field _bscan_tunnel_nested_tap_select_dmi[] = { } }; struct scan_field *bscan_tunnel_nested_tap_select_dmi = _bscan_tunnel_nested_tap_select_dmi; -uint32_t bscan_tunnel_nested_tap_select_dmi_num_fields = DIM(_bscan_tunnel_nested_tap_select_dmi); +uint32_t bscan_tunnel_nested_tap_select_dmi_num_fields = ARRAY_SIZE(_bscan_tunnel_nested_tap_select_dmi); struct scan_field *bscan_tunnel_data_register_select_dmi = _bscan_tunnel_data_register_select_dmi; -uint32_t bscan_tunnel_data_register_select_dmi_num_fields = DIM(_bscan_tunnel_data_register_select_dmi); +uint32_t bscan_tunnel_data_register_select_dmi_num_fields = ARRAY_SIZE(_bscan_tunnel_data_register_select_dmi); struct trigger { uint64_t address; @@ -352,8 +350,8 @@ uint32_t dtmcontrol_scan_via_bscan(struct target *target, uint32_t out) tunneled_dr[0].in_value = NULL; } jtag_add_ir_scan(target->tap, &select_user4, TAP_IDLE); - jtag_add_dr_scan(target->tap, DIM(tunneled_ir), tunneled_ir, TAP_IDLE); - jtag_add_dr_scan(target->tap, DIM(tunneled_dr), tunneled_dr, TAP_IDLE); + jtag_add_dr_scan(target->tap, ARRAY_SIZE(tunneled_ir), tunneled_ir, TAP_IDLE); + jtag_add_dr_scan(target->tap, ARRAY_SIZE(tunneled_dr), tunneled_dr, TAP_IDLE); select_dmi_via_bscan(target); int retval = jtag_execute_queue(); @@ -1849,7 +1847,7 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params, GDB_REGNO_PC, GDB_REGNO_MSTATUS, GDB_REGNO_MEPC, GDB_REGNO_MCAUSE, }; - for (unsigned i = 0; i < DIM(regnums); i++) { + for (unsigned i = 0; i < ARRAY_SIZE(regnums); i++) { enum gdb_regno regno = regnums[i]; riscv_reg_t reg_value; if (riscv_get_register(target, ®_value, regno) != ERROR_OK) @@ -4152,7 +4150,7 @@ int riscv_init_registers(struct target *target) #undef DECLARE_CSR }; /* encoding.h does not contain the registers in sorted order. */ - qsort(csr_info, DIM(csr_info), sizeof(*csr_info), cmp_csr_info); + qsort(csr_info, ARRAY_SIZE(csr_info), sizeof(*csr_info), cmp_csr_info); unsigned csr_info_index = 0; int custom_within_range = 0; @@ -4411,7 +4409,7 @@ int riscv_init_registers(struct target *target) unsigned csr_number = number - GDB_REGNO_CSR0; while (csr_info[csr_info_index].number < csr_number && - csr_info_index < DIM(csr_info) - 1) { + csr_info_index < ARRAY_SIZE(csr_info) - 1) { csr_info_index++; } if (csr_info[csr_info_index].number == csr_number) { -- cgit v1.1